1 /* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
\r
2 º TITLE: RTL8019AS ethernet routines for 8051 and º
\r
3 º Keil C51 v7.00 port of Adam Dunkels' uIP v0.9 º
\r
4 º FILENAME: etherdev.h º
\r
5 º REVISION: VER 0.0 º
\r
6 º REV.DATE: 21-01-05 º
\r
8 º AUTHOR: Copyright (c) 2005, Murray R. Van Luyn. º
\r
9 ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */
\r
11 /* ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿
\r
12 ³ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS ³
\r
13 ³ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ³
\r
14 ³ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ³
\r
15 ³ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY ³
\r
16 ³ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ³
\r
17 ³ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ³
\r
18 ³ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ³
\r
19 ³ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ³
\r
20 ³ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ³
\r
21 ³ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ³
\r
22 ³ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ³
\r
23 ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ */
\r
31 extern unsigned char uip_buf[64];
\r
32 extern unsigned int uip_len;
\r
35 /* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
\r
39 ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */
\r
40 // Change ETH_CPU_XTAL to match hardware
\r
41 #define ETH_CPU_XTAL 24000000 // 8051 crystal freq in Hz
\r
44 /* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
\r
46 º ISA Expansion slot signal to 8051 port mapping. º
\r
48 ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */
\r
49 #define ETH_DATA_PORT P2 // Adjust this to suit hardware.
\r
50 #define ETH_ADDR_PORT P1 // Adjust this to suit hardware.
\r
51 #define ETH_CTRL_PORT P3 // Adjust this to suit hardware.
\r
52 sbit IOW = ETH_CTRL_PORT^4; // ISA slot pin B13, RTL8019AS pin 30, active low
\r
53 sbit IOR = ETH_CTRL_PORT^5; // ISA slot pin B14, RTL8019AS pin 29, active low
\r
54 sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red
\r
57 /* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
\r
59 º Required additional ISA slot wiring. º
\r
61 ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */
\r
62 // SD0 ETH_DATA_PORT^0 // ISA slot pin A9, RTL8019AS pin 36
\r
63 // SD1 ETH_DATA_PORT^1 // ISA slot pin A8, RTL8019AS pin 37
\r
64 // SD2 ETH_DATA_PORT^2 // ISA slot pin A7, RTL8019AS pin 38
\r
65 // SD3 ETH_DATA_PORT^3 // ISA slot pin A6, RTL8019AS pin 39
\r
66 // SD4 ETH_DATA_PORT^4 // ISA slot pin A5, RTL8019AS pin 40
\r
67 // SD5 ETH_DATA_PORT^5 // ISA slot pin A4, RTL8019AS pin 41
\r
68 // SD6 ETH_DATA_PORT^6 // ISA slot pin A3, RTL8019AS pin 42
\r
69 // SD7 ETH_DATA_PORT^7 // ISA slot pin A2, RTL8019AS pin 43
\r
70 // SA0 ETH_ADDR_PORT^0 // ISA slot pin A31, RTL8019AS pin 5
\r
71 // SA1 ETH_ADDR_PORT^1 // ISA slot pin A30, RTL8019AS pin 7
\r
72 // SA2 ETH_ADDR_PORT^2 // ISA slot pin A29, RTL8019AS pin 8
\r
73 // SA3 ETH_ADDR_PORT^3 // ISA slot pin A28, RTL8019AS pin 9
\r
74 // SA4 ETH_ADDR_PORT^4 // ISA slot pin A27, RTL8019AS pin 10
\r
75 // SA5 GND // ISA slot pin A26, RTL8019AS pin 11
\r
76 // SA6 GND // ISA slot pin A25, RTL8019AS pin 12
\r
77 // SA7 GND // ISA slot pin A24, RTL8019AS pin 13
\r
78 // SA8 +5V // ISA slot pin A23, RTL8019AS pin 15
\r
79 // SA9 +5V // ISA slot pin A22, RTL8019AS pin 16
\r
80 // SA10 GND // ISA slot pin A21, RTL8019AS pin 18
\r
81 // SA11 GND // ISA slot pin A20, RTL8019AS pin 19
\r
82 // SA12 GND // ISA slot pin A19, RTL8019AS pin 20
\r
83 // SA13 GND // ISA slot pin A18, RTL8019AS pin 21
\r
84 // SA14 GND // ISA slot pin A17, RTL8019AS pin 22
\r
85 // SA15 GND // ISA slot pin A16, RTL8019AS pin 23
\r
86 // SA16 GND // ISA slot pin A15, RTL8019AS pin 24
\r
87 // SA17 GND // ISA slot pin A14, RTL8019AS pin 25
\r
88 // SA18 GND // ISA slot pin A13, RTL8019AS pin 26
\r
89 // SA19 GND // ISA slot pin A12, RTL8019AS pin 27
\r
90 // AEN GND // ISA slot pin A11, RTL8019AS pin 34
\r
91 // SMEMW +5V // ISA slot pin B11, RTL8019AS pin 32
\r
92 // SMEMR +5V // ISA slot pin B12, RTL8019AS pin 31
\r
93 // GND GND // ISA slot pin B1
\r
94 // +5VDC +5V // ISA slot pin B3
\r
95 // GND GND // ISA slot pin B31
\r
96 // +5VDC +5V // ISA slot pin B29
\r
97 // RESET ? // ISA slot pin B2, active high reset input
\r
100 /* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
\r
102 º ISA 16 bit expansion slot edge connector. º
\r
104 ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */
\r
107 // ³C18 C1³ ³A31 Component side A1³
\r
108 // ÔÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ; ÔÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ;
\r
109 // D18 D1 B31 Solder side B1
\r
113 /* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
\r
115 º RTL8019AS Register defines. º
\r
117 ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */
\r
119 // Register base address
\r
120 #define ETH_REG_BASE 0x0000 // Hardwired to 0x0300
\r
122 // Registers common to all pages.
\r
123 #define CR ETH_REG_BASE + 0x00 // Control register
\r
124 // Control register bits
\r
125 #define PS1 0x80 // Page select bit 1
\r
126 #define PS0 0x40 // Page select bit 0
\r
127 #define RD2 0x20 // Remote DMA control bit 2
\r
128 #define RD1 0x10 // Remote DMA control bit 1
\r
129 #define RD0 0x08 // Remote DMA control bit 0
\r
130 #define TXP 0x04 // Transmit packet bit
\r
131 #define STA 0x02 // Start bit (a flag only)
\r
132 #define STP 0x01 // Stop bit transceiver ctrl
\r
133 #define RDMA 0x10 // Remote DMA port
\r
134 #define RESET 0x18 // Reset port
\r
136 // Page 0 read/write registers.
\r
137 #define BNRY ETH_REG_BASE + 0x03 // Boundary register
\r
138 #define ISR ETH_REG_BASE + 0x07 // Interrupt status register
\r
139 // Interrupt status register bits
\r
140 #define RST 0x80 // Reset state indicator bit
\r
141 #define RDC 0x40 // Remote DMA complete bit
\r
142 #define CNT 0x20 // Network tally counter MSB set
\r
143 #define OVW 0x10 // Receive buffer exhausted
\r
144 #define TXE 0x08 // Transmit abort error bit
\r
145 #define RXE 0x04 // Receive error report bit
\r
146 #define PTX 0x02 // Successful packet transmit
\r
147 #define PRX 0x01 // Successful packet receive
\r
149 // Page 0 read only registers.
\r
150 #define CLDA0 ETH_REG_BASE + 0x01
\r
151 #define CLDA1 ETH_REG_BASE + 0x02
\r
152 #define TSR ETH_REG_BASE + 0x04
\r
153 #define NCR ETH_REG_BASE + 0x05
\r
154 #define FIFO ETH_REG_BASE + 0x06
\r
155 #define CRDA0 ETH_REG_BASE + 0x08
\r
156 #define CRDA1 ETH_REG_BASE + 0x09
\r
157 #define _8019ID0 ETH_REG_BASE + 0x0A
\r
158 #define _8019ID1 ETH_REG_BASE + 0x0B
\r
159 #define RSR ETH_REG_BASE + 0x0C
\r
160 #define CNTR0 ETH_REG_BASE + 0x0D
\r
161 #define CNTR1 ETH_REG_BASE + 0x0E
\r
162 #define CNTR2 ETH_REG_BASE + 0x0F
\r
164 // Page 0 write only registers.
\r
165 #define PSTART ETH_REG_BASE + 0x01 // Receive page start register
\r
166 #define PSTOP ETH_REG_BASE + 0x02 // Receive page stop register
\r
167 #define TPSR ETH_REG_BASE + 0x04 // Transmit page start register
\r
168 #define TBCR0 ETH_REG_BASE + 0x05 // Transmit byte count register 0
\r
169 #define TBCR1 ETH_REG_BASE + 0x06 // Transmit byte count register 1
\r
170 #define RSAR0 ETH_REG_BASE + 0x08 // Remote start address register 0
\r
171 #define RSAR1 ETH_REG_BASE + 0x09 // Remote start address register 0
\r
172 #define RBCR0 ETH_REG_BASE + 0x0A // Remote byte count register 0
\r
173 #define RBCR1 ETH_REG_BASE + 0x0B // Remote byte count register 1
\r
174 #define RCR ETH_REG_BASE + 0x0C // Receive configuration register
\r
175 // Receive configuration register bits (write in page 0, read in page 2)
\r
176 #define MON 0x20 // Monitor mode select bit
\r
177 #define PRO 0x10 // Promiscuous mode select bit
\r
178 #define AM 0x08 // Multicast packet accept bit
\r
179 #define AB 0x04 // Broadcast packet accept bit
\r
180 #define AR 0x02 // Runt packet accept bit
\r
181 #define SEP 0x01 // Error packet accept bit
\r
182 #define TCR ETH_REG_BASE + 0x0D // Transmit configuration register
\r
183 // Transmit configuration register bits
\r
184 #define OFST 0x10 // Collision offset enable bit
\r
185 #define ATD 0x08 // Auto transmit disable select bit
\r
186 #define LB1 0x04 // Loopback mode select bit 1
\r
187 #define LB0 0x02 // Loopback mode select bit 0
\r
188 #define CRC 0x01 // CRC generation inhibit bit
\r
189 #define DCR ETH_REG_BASE + 0x0E // Data configuration register
\r
190 // Data configuration register bits (write in page 0, read in page 2)
\r
191 #define FT1 0x40 // FIFO threshold select bit 1
\r
192 #define FT0 0x20 // FIFO threshold select bit 0
\r
193 #define ARM 0x10 // Auto-initialise remote
\r
194 #define LS 0x08 // Loopback select bit
\r
195 #define LAS 0x04 // Set to 0 (pwrup = 1)
\r
196 #define BOS 0x02 // Byte order select bit
\r
197 #define WTS 0x01 // Word transfer select bit
\r
198 #define IMR ETH_REG_BASE + 0x0F // Interrupt mask register
\r
199 // Interrupt mask register bits
\r
200 // Each enable bit correspons with an interrupt flag in ISR
\r
202 // Page 1 read/write registers.
\r
203 #define PAR0 ETH_REG_BASE + 0x01 // Physical address register 0
\r
204 #define PAR1 ETH_REG_BASE + 0x02 // Physical address register 1
\r
205 #define PAR2 ETH_REG_BASE + 0x03 // Physical address register 2
\r
206 #define PAR3 ETH_REG_BASE + 0x04 // Physical address register 3
\r
207 #define PAR4 ETH_REG_BASE + 0x05 // Physical address register 4
\r
208 #define PAR5 ETH_REG_BASE + 0x06 // Physical address register 5
\r
209 #define CURR ETH_REG_BASE + 0x07 // Current receive buffer page
\r
210 #define MAR0 ETH_REG_BASE + 0x08
\r
211 #define MAR1 ETH_REG_BASE + 0x09
\r
212 #define MAR2 ETH_REG_BASE + 0x0A
\r
213 #define MAR3 ETH_REG_BASE + 0x0B
\r
214 #define MAR4 ETH_REG_BASE + 0x0C
\r
215 #define MAR5 ETH_REG_BASE + 0x0D
\r
216 #define MAR6 ETH_REG_BASE + 0x0E
\r
217 #define MAR7 ETH_REG_BASE + 0x0F
\r
219 // Page 2 read only registers.
\r
220 // Each previously defined in page 0 write only.
\r
221 //#define PSTART ETH_REG_BASE + 0x01
\r
222 //#define PSTOP ETH_REG_BASE + 0x02
\r
223 //#define TPSR ETH_REG_BASE + 0x04
\r
224 //#define RCR ETH_REG_BASE + 0x0C
\r
225 //#define TCR ETH_REG_BASE + 0x0D
\r
226 //#define DCR ETH_REG_BASE + 0x0E
\r
227 //#define IMR ETH_REG_BASE + 0x0F
\r
229 // Page 3 read/write registers.
\r
230 #define _9346CR ETH_REG_BASE + 0x01 // 9346 EEPROM command register
\r
231 // 9346 EEPROM command register bits
\r
232 #define EEM1 0x80 // RTL8019AS operating mode bit 1
\r
233 #define EEM0 0x40 // RTL8019AS operating mode bit 0
\r
234 #define EECS 0x08 // 9346 EEPROM chip select bit
\r
235 #define EESK 0x04 // 9346 EEPROM serial clock bit
\r
236 #define EEDI 0x02 // 9346 EEPROM data input bit
\r
237 #define EEDO 0x01 // 9346 EEPROM data output bit
\r
238 #define BPAGE ETH_REG_BASE + 0x02
\r
239 #define CONFIG1 ETH_REG_BASE + 0x04 // RTL9019AS config register 1
\r
240 // RTL9019AS config register 1 bits
\r
241 #define IRQEN 0x80 // IRQ enable bit (WR protected)
\r
242 #define IRQS2 0x40 // IRQ line select bit 2
\r
243 #define IRQS1 0x20 // IRQ line select bit 1
\r
244 #define IRQS0 0x10 // IRQ line select bit 0
\r
245 #define IOS3 0x08 // I/O base address select bit 3
\r
246 #define IOS2 0x04 // I/O base address select bit 2
\r
247 #define IOS1 0x02 // I/O base address select bit 1
\r
248 #define IOS0 0x01 // I/O base address select bit 0
\r
249 #define CONFIG2 ETH_REG_BASE + 0x05 //
\r
250 // RTL9019AS config register 2 bits
\r
251 #define PL1 0x80 // Network medium type select bit 1
\r
252 #define PL0 0x40 // Network medium type select bit 0
\r
253 #define BSELB 0x20 // Boot ROM disable (WR protected)
\r
254 #define BS4 0x10 // Boot ROM configuration bit 4
\r
255 #define BS3 0x08 // Boot ROM configuration bit 3
\r
256 #define BS2 0x04 // Boot ROM configuration bit 2
\r
257 #define BS1 0x02 // Boot ROM configuration bit 1
\r
258 #define BS0 0x01 // Boot ROM configuration bit 0
\r
259 #define CONFIG3 ETH_REG_BASE + 0x06 // RTL9019AS config register 3
\r
260 // RTL9019AS config register 3 bits
\r
261 #define PNP 0x80 // Plug & play mode indicator bit
\r
262 #define FUDUP 0x40 // Full duplex mode select bit
\r
263 #define LEDS1 0x20 // LED output select bit 1
\r
264 #define LEDS0 0x10 // LED output select bit 0
\r
265 #define SLEEP 0x04 // Sleep mode select bit
\r
266 #define PWRDN 0x02 // Power down mode select bit
\r
267 #define ACTIVEB 0x01 // Inverse of bit 0, PNP active reg
\r
269 // Page 3 read only registers.
\r
270 #define CONFIG0 ETH_REG_BASE + 0x03 // RTL9019AS config register 0
\r
271 // RTL9019AS config register 0 bits
\r
272 #define VERID1 0x80 // RTL9019AS version ID bit 1 (R/W)
\r
273 #define VERID0 0x40 // RTL9019AS version ID bit 0 (R/W)
\r
274 #define AUI 0x20 // AUI input pin state bit
\r
275 #define PNPJP 0x10 // PNP jumper pin state bit
\r
276 #define JP 0x08 // JP input pin state bit
\r
277 #define BNC 0x04 // Thinnet mode indication bit
\r
278 #define CSNSAV ETH_REG_BASE + 0x08
\r
279 #define INTR ETH_REG_BASE + 0x0B
\r
280 #define CONFIG4 ETH_REG_BASE + 0x0D
\r
282 // Page 3 write only registers.
\r
283 #define TEST ETH_REG_BASE + 0x07
\r
284 #define HLTCLK ETH_REG_BASE + 0x09
\r
285 #define FMWP ETH_REG_BASE + 0x0C
\r
290 /* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»
\r
291 º Public Function Prototypes º
\r
292 ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */
\r
293 bit etherdev_init(void);
\r
294 void etherdev_send(void);
\r
295 unsigned int etherdev_read(void);
\r
projects / z.facultad / 66.09 / etherled.git / blob