// Each enable bit correspons with an interrupt flag in ISR
// Page 1 read/write registers.
+#define PAR_BASE REG_BASE + 0x01 // Physical address register base address
#define PAR0 REG_BASE + 0x01 // Physical address register 0
#define PAR1 REG_BASE + 0x02 // Physical address register 1
#define PAR2 REG_BASE + 0x03 // Physical address register 2