-/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
- º TITLE: RTL8019AS ethernet routines for 8051 and º\r
- º Keil C51 v7.00 port of Adam Dunkels' uIP v0.9 º\r
- º FILENAME: etherdev.h º\r
- º REVISION: VER 0.0 º\r
- º REV.DATE: 21-01-05 º\r
- º ARCHIVE: º\r
- º AUTHOR: Copyright (c) 2005, Murray R. Van Luyn. º\r
- ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
-\r
-/* ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿\r
- ³ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS ³ \r
- ³ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ³ \r
- ³ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ³ \r
- ³ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY ³ \r
- ³ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ³ \r
- ³ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ³ \r
- ³ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ³ \r
- ³ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ³ \r
- ³ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ³ \r
- ³ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ³ \r
- ³ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ³ \r
- ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ */\r
-\r
-\r
-#ifndef ETHERDEV_H\r
-#define ETHERDEV_H\r
-\r
-#include "REG51.h"\r
-\r
-extern unsigned char uip_buf[64];\r
-extern unsigned int uip_len;\r
-\r
-\r
-/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
- º º\r
- º Public defines. º\r
- º º\r
- ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
-// Change ETH_CPU_XTAL to match hardware\r
-#define ETH_CPU_XTAL 24000000 // 8051 crystal freq in Hz\r
-\r
-\r
-/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
- º º\r
- º ISA Expansion slot signal to 8051 port mapping. º\r
- º º\r
- ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
-#define ETH_DATA_PORT P2 // Adjust this to suit hardware.\r
-#define ETH_ADDR_PORT P1 // Adjust this to suit hardware.\r
-#define ETH_CTRL_PORT P3 // Adjust this to suit hardware.\r
-sbit IOW = ETH_CTRL_PORT^4; // ISA slot pin B13, RTL8019AS pin 30, active low\r
-sbit IOR = ETH_CTRL_PORT^5; // ISA slot pin B14, RTL8019AS pin 29, active low\r
-sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red\r
-\r
-\r
-/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
- º º\r
- º Required additional ISA slot wiring. º\r
- º º\r
- ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
-// SD0 ETH_DATA_PORT^0 // ISA slot pin A9, RTL8019AS pin 36\r
-// SD1 ETH_DATA_PORT^1 // ISA slot pin A8, RTL8019AS pin 37\r
-// SD2 ETH_DATA_PORT^2 // ISA slot pin A7, RTL8019AS pin 38\r
-// SD3 ETH_DATA_PORT^3 // ISA slot pin A6, RTL8019AS pin 39\r
-// SD4 ETH_DATA_PORT^4 // ISA slot pin A5, RTL8019AS pin 40\r
-// SD5 ETH_DATA_PORT^5 // ISA slot pin A4, RTL8019AS pin 41\r
-// SD6 ETH_DATA_PORT^6 // ISA slot pin A3, RTL8019AS pin 42\r
-// SD7 ETH_DATA_PORT^7 // ISA slot pin A2, RTL8019AS pin 43\r
-// SA0 ETH_ADDR_PORT^0 // ISA slot pin A31, RTL8019AS pin 5\r
-// SA1 ETH_ADDR_PORT^1 // ISA slot pin A30, RTL8019AS pin 7\r
-// SA2 ETH_ADDR_PORT^2 // ISA slot pin A29, RTL8019AS pin 8\r
-// SA3 ETH_ADDR_PORT^3 // ISA slot pin A28, RTL8019AS pin 9\r
-// SA4 ETH_ADDR_PORT^4 // ISA slot pin A27, RTL8019AS pin 10\r
-// SA5 GND // ISA slot pin A26, RTL8019AS pin 11\r
-// SA6 GND // ISA slot pin A25, RTL8019AS pin 12\r
-// SA7 GND // ISA slot pin A24, RTL8019AS pin 13\r
-// SA8 +5V // ISA slot pin A23, RTL8019AS pin 15\r
-// SA9 +5V // ISA slot pin A22, RTL8019AS pin 16\r
-// SA10 GND // ISA slot pin A21, RTL8019AS pin 18\r
-// SA11 GND // ISA slot pin A20, RTL8019AS pin 19\r
-// SA12 GND // ISA slot pin A19, RTL8019AS pin 20\r
-// SA13 GND // ISA slot pin A18, RTL8019AS pin 21\r
-// SA14 GND // ISA slot pin A17, RTL8019AS pin 22\r
-// SA15 GND // ISA slot pin A16, RTL8019AS pin 23\r
-// SA16 GND // ISA slot pin A15, RTL8019AS pin 24\r
-// SA17 GND // ISA slot pin A14, RTL8019AS pin 25\r
-// SA18 GND // ISA slot pin A13, RTL8019AS pin 26\r
-// SA19 GND // ISA slot pin A12, RTL8019AS pin 27\r
-// AEN GND // ISA slot pin A11, RTL8019AS pin 34\r
-// SMEMW +5V // ISA slot pin B11, RTL8019AS pin 32\r
-// SMEMR +5V // ISA slot pin B12, RTL8019AS pin 31\r
-// GND GND // ISA slot pin B1\r
-// +5VDC +5V // ISA slot pin B3\r
-// GND GND // ISA slot pin B31\r
-// +5VDC +5V // ISA slot pin B29\r
-// RESET ? // ISA slot pin B2, active high reset input\r
-\r
-\r
-/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
- º º\r
- º ISA 16 bit expansion slot edge connector. º\r
- º º\r
- ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
-\r
-// ³ ÚÄÄÄÄÄ¿ ³\r
-// ³C18 C1³ ³A31 Component side A1³\r
-// ÔÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ; ÔÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ; \r
-// D18 D1 B31 Solder side B1\r
-\r
-\r
-\r
-/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
- º º\r
- º RTL8019AS Register defines. º\r
- º º\r
- ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
-\r
-// Register base address\r
-#define ETH_REG_BASE 0x0000 // Hardwired to 0x0300\r
-\r
-// Registers common to all pages.\r
-#define CR ETH_REG_BASE + 0x00 // Control register\r
- // Control register bits\r
- #define PS1 0x80 // Page select bit 1\r
- #define PS0 0x40 // Page select bit 0\r
- #define RD2 0x20 // Remote DMA control bit 2\r
- #define RD1 0x10 // Remote DMA control bit 1\r
- #define RD0 0x08 // Remote DMA control bit 0\r
- #define TXP 0x04 // Transmit packet bit\r
- #define STA 0x02 // Start bit (a flag only)\r
- #define STP 0x01 // Stop bit transceiver ctrl\r
-#define RDMA 0x10 // Remote DMA port\r
-#define RESET 0x18 // Reset port\r
-\r
-// Page 0 read/write registers.\r
-#define BNRY ETH_REG_BASE + 0x03 // Boundary register\r
-#define ISR ETH_REG_BASE + 0x07 // Interrupt status register\r
- // Interrupt status register bits\r
- #define RST 0x80 // Reset state indicator bit\r
- #define RDC 0x40 // Remote DMA complete bit\r
- #define CNT 0x20 // Network tally counter MSB set\r
- #define OVW 0x10 // Receive buffer exhausted\r
- #define TXE 0x08 // Transmit abort error bit\r
- #define RXE 0x04 // Receive error report bit\r
- #define PTX 0x02 // Successful packet transmit\r
- #define PRX 0x01 // Successful packet receive\r
-\r
-// Page 0 read only registers.\r
-#define CLDA0 ETH_REG_BASE + 0x01\r
-#define CLDA1 ETH_REG_BASE + 0x02\r
-#define TSR ETH_REG_BASE + 0x04\r
-#define NCR ETH_REG_BASE + 0x05\r
-#define FIFO ETH_REG_BASE + 0x06\r
-#define CRDA0 ETH_REG_BASE + 0x08\r
-#define CRDA1 ETH_REG_BASE + 0x09\r
-#define _8019ID0 ETH_REG_BASE + 0x0A\r
-#define _8019ID1 ETH_REG_BASE + 0x0B\r
-#define RSR ETH_REG_BASE + 0x0C\r
-#define CNTR0 ETH_REG_BASE + 0x0D\r
-#define CNTR1 ETH_REG_BASE + 0x0E\r
-#define CNTR2 ETH_REG_BASE + 0x0F\r
-\r
-// Page 0 write only registers.\r
-#define PSTART ETH_REG_BASE + 0x01 // Receive page start register\r
-#define PSTOP ETH_REG_BASE + 0x02 // Receive page stop register\r
-#define TPSR ETH_REG_BASE + 0x04 // Transmit page start register\r
-#define TBCR0 ETH_REG_BASE + 0x05 // Transmit byte count register 0\r
-#define TBCR1 ETH_REG_BASE + 0x06 // Transmit byte count register 1\r
-#define RSAR0 ETH_REG_BASE + 0x08 // Remote start address register 0\r
-#define RSAR1 ETH_REG_BASE + 0x09 // Remote start address register 0\r
-#define RBCR0 ETH_REG_BASE + 0x0A // Remote byte count register 0\r
-#define RBCR1 ETH_REG_BASE + 0x0B // Remote byte count register 1\r
-#define RCR ETH_REG_BASE + 0x0C // Receive configuration register\r
- // Receive configuration register bits (write in page 0, read in page 2)\r
- #define MON 0x20 // Monitor mode select bit\r
- #define PRO 0x10 // Promiscuous mode select bit\r
- #define AM 0x08 // Multicast packet accept bit\r
- #define AB 0x04 // Broadcast packet accept bit\r
- #define AR 0x02 // Runt packet accept bit\r
- #define SEP 0x01 // Error packet accept bit\r
-#define TCR ETH_REG_BASE + 0x0D // Transmit configuration register\r
- // Transmit configuration register bits\r
- #define OFST 0x10 // Collision offset enable bit\r
- #define ATD 0x08 // Auto transmit disable select bit\r
- #define LB1 0x04 // Loopback mode select bit 1\r
- #define LB0 0x02 // Loopback mode select bit 0\r
- #define CRC 0x01 // CRC generation inhibit bit\r
-#define DCR ETH_REG_BASE + 0x0E // Data configuration register\r
- // Data configuration register bits (write in page 0, read in page 2)\r
- #define FT1 0x40 // FIFO threshold select bit 1\r
- #define FT0 0x20 // FIFO threshold select bit 0\r
- #define ARM 0x10 // Auto-initialise remote\r
- #define LS 0x08 // Loopback select bit\r
- #define LAS 0x04 // Set to 0 (pwrup = 1)\r
- #define BOS 0x02 // Byte order select bit\r
- #define WTS 0x01 // Word transfer select bit\r
-#define IMR ETH_REG_BASE + 0x0F // Interrupt mask register\r
- // Interrupt mask register bits\r
- // Each enable bit correspons with an interrupt flag in ISR\r
-\r
-// Page 1 read/write registers.\r
-#define PAR0 ETH_REG_BASE + 0x01 // Physical address register 0\r
-#define PAR1 ETH_REG_BASE + 0x02 // Physical address register 1\r
-#define PAR2 ETH_REG_BASE + 0x03 // Physical address register 2\r
-#define PAR3 ETH_REG_BASE + 0x04 // Physical address register 3\r
-#define PAR4 ETH_REG_BASE + 0x05 // Physical address register 4\r
-#define PAR5 ETH_REG_BASE + 0x06 // Physical address register 5\r
-#define CURR ETH_REG_BASE + 0x07 // Current receive buffer page\r
-#define MAR0 ETH_REG_BASE + 0x08\r
-#define MAR1 ETH_REG_BASE + 0x09\r
-#define MAR2 ETH_REG_BASE + 0x0A\r
-#define MAR3 ETH_REG_BASE + 0x0B\r
-#define MAR4 ETH_REG_BASE + 0x0C\r
-#define MAR5 ETH_REG_BASE + 0x0D\r
-#define MAR6 ETH_REG_BASE + 0x0E\r
-#define MAR7 ETH_REG_BASE + 0x0F\r
-\r
-// Page 2 read only registers.\r
-// Each previously defined in page 0 write only.\r
-//#define PSTART ETH_REG_BASE + 0x01\r
-//#define PSTOP ETH_REG_BASE + 0x02\r
-//#define TPSR ETH_REG_BASE + 0x04\r
-//#define RCR ETH_REG_BASE + 0x0C\r
-//#define TCR ETH_REG_BASE + 0x0D\r
-//#define DCR ETH_REG_BASE + 0x0E\r
-//#define IMR ETH_REG_BASE + 0x0F\r
-\r
-// Page 3 read/write registers.\r
-#define _9346CR ETH_REG_BASE + 0x01 // 9346 EEPROM command register\r
- // 9346 EEPROM command register bits\r
- #define EEM1 0x80 // RTL8019AS operating mode bit 1\r
- #define EEM0 0x40 // RTL8019AS operating mode bit 0\r
- #define EECS 0x08 // 9346 EEPROM chip select bit\r
- #define EESK 0x04 // 9346 EEPROM serial clock bit\r
- #define EEDI 0x02 // 9346 EEPROM data input bit\r
- #define EEDO 0x01 // 9346 EEPROM data output bit\r
-#define BPAGE ETH_REG_BASE + 0x02\r
-#define CONFIG1 ETH_REG_BASE + 0x04 // RTL9019AS config register 1\r
- // RTL9019AS config register 1 bits\r
- #define IRQEN 0x80 // IRQ enable bit (WR protected)\r
- #define IRQS2 0x40 // IRQ line select bit 2\r
- #define IRQS1 0x20 // IRQ line select bit 1\r
- #define IRQS0 0x10 // IRQ line select bit 0\r
- #define IOS3 0x08 // I/O base address select bit 3\r
- #define IOS2 0x04 // I/O base address select bit 2\r
- #define IOS1 0x02 // I/O base address select bit 1\r
- #define IOS0 0x01 // I/O base address select bit 0\r
-#define CONFIG2 ETH_REG_BASE + 0x05 // \r
- // RTL9019AS config register 2 bits\r
- #define PL1 0x80 // Network medium type select bit 1\r
- #define PL0 0x40 // Network medium type select bit 0\r
- #define BSELB 0x20 // Boot ROM disable (WR protected)\r
- #define BS4 0x10 // Boot ROM configuration bit 4\r
- #define BS3 0x08 // Boot ROM configuration bit 3\r
- #define BS2 0x04 // Boot ROM configuration bit 2\r
- #define BS1 0x02 // Boot ROM configuration bit 1\r
- #define BS0 0x01 // Boot ROM configuration bit 0\r
-#define CONFIG3 ETH_REG_BASE + 0x06 // RTL9019AS config register 3\r
- // RTL9019AS config register 3 bits\r
- #define PNP 0x80 // Plug & play mode indicator bit\r
- #define FUDUP 0x40 // Full duplex mode select bit\r
- #define LEDS1 0x20 // LED output select bit 1\r
- #define LEDS0 0x10 // LED output select bit 0\r
- #define SLEEP 0x04 // Sleep mode select bit\r
- #define PWRDN 0x02 // Power down mode select bit\r
- #define ACTIVEB 0x01 // Inverse of bit 0, PNP active reg\r
-\r
-// Page 3 read only registers.\r
-#define CONFIG0 ETH_REG_BASE + 0x03 // RTL9019AS config register 0\r
- // RTL9019AS config register 0 bits\r
- #define VERID1 0x80 // RTL9019AS version ID bit 1 (R/W)\r
- #define VERID0 0x40 // RTL9019AS version ID bit 0 (R/W)\r
- #define AUI 0x20 // AUI input pin state bit\r
- #define PNPJP 0x10 // PNP jumper pin state bit\r
- #define JP 0x08 // JP input pin state bit\r
- #define BNC 0x04 // Thinnet mode indication bit\r
-#define CSNSAV ETH_REG_BASE + 0x08\r
-#define INTR ETH_REG_BASE + 0x0B\r
-#define CONFIG4 ETH_REG_BASE + 0x0D\r
-\r
-// Page 3 write only registers.\r
-#define TEST ETH_REG_BASE + 0x07\r
-#define HLTCLK ETH_REG_BASE + 0x09\r
-#define FMWP ETH_REG_BASE + 0x0C\r
-\r
-\r
-\r
-\r
-/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
- º Public Function Prototypes º\r
- ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
-bit etherdev_init(void);\r
-void etherdev_send(void);\r
-unsigned int etherdev_read(void);\r
-\r
-#endif\r
+// vim: set et sw=4 sts=4 :
+
+#ifndef ETHERDEV_H
+#define ETHERDEV_H
+
+#include "REG51.h"
+
+extern unsigned char uip_buf[80];
+extern unsigned int uip_len;
+
+
+#define ETH_DATA_PORT P2 // Adjust this to suit hardware.
+#define ETH_ADDR_PORT P1 // Adjust this to suit hardware.
+#define ETH_CTRL_PORT P3 // Adjust this to suit hardware.
+sbit IOW = ETH_CTRL_PORT^4; // ISA slot pin B13, RTL8019AS pin 30, active low
+sbit IOR = ETH_CTRL_PORT^5; // ISA slot pin B14, RTL8019AS pin 29, active low
+sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red
+
+
+// Register base address
+#define ETH_REG_BASE 0x0000 // Hardwired to 0x0300
+
+// Registers common to all pages.
+#define CR ETH_REG_BASE + 0x00 // Control register
+ // Control register bits
+ #define PS1 0x80 // Page select bit 1
+ #define PS0 0x40 // Page select bit 0
+ #define RD2 0x20 // Remote DMA control bit 2
+ #define RD1 0x10 // Remote DMA control bit 1
+ #define RD0 0x08 // Remote DMA control bit 0
+ #define TXP 0x04 // Transmit packet bit
+ #define STA 0x02 // Start bit (a flag only)
+ #define STP 0x01 // Stop bit transceiver ctrl
+#define RDMA 0x10 // Remote DMA port
+#define RESET 0x18 // Reset port
+
+// Page 0 read/write registers.
+#define BNRY ETH_REG_BASE + 0x03 // Boundary register
+#define ISR ETH_REG_BASE + 0x07 // Interrupt status register
+ // Interrupt status register bits
+ #define RST 0x80 // Reset state indicator bit
+ #define RDC 0x40 // Remote DMA complete bit
+ #define CNT 0x20 // Network tally counter MSB set
+ #define OVW 0x10 // Receive buffer exhausted
+ #define TXE 0x08 // Transmit abort error bit
+ #define RXE 0x04 // Receive error report bit
+ #define PTX 0x02 // Successful packet transmit
+ #define PRX 0x01 // Successful packet receive
+
+// Page 0 read only registers.
+#define CLDA0 ETH_REG_BASE + 0x01
+#define CLDA1 ETH_REG_BASE + 0x02
+#define TSR ETH_REG_BASE + 0x04
+#define NCR ETH_REG_BASE + 0x05
+#define FIFO ETH_REG_BASE + 0x06
+#define CRDA0 ETH_REG_BASE + 0x08
+#define CRDA1 ETH_REG_BASE + 0x09
+#define CONFIGA ETH_REG_BASE + 0x0A
+#define CONFIGB ETH_REG_BASE + 0x0B
+#define RSR ETH_REG_BASE + 0x0C
+#define CNTR0 ETH_REG_BASE + 0x0D
+#define CNTR1 ETH_REG_BASE + 0x0E
+#define CNTR2 ETH_REG_BASE + 0x0F
+
+// Page 0 write only registers.
+#define PSTART ETH_REG_BASE + 0x01 // Receive page start register
+#define PSTOP ETH_REG_BASE + 0x02 // Receive page stop register
+#define TPSR ETH_REG_BASE + 0x04 // Transmit page start register
+#define TBCR0 ETH_REG_BASE + 0x05 // Transmit byte count register 0
+#define TBCR1 ETH_REG_BASE + 0x06 // Transmit byte count register 1
+#define RSAR0 ETH_REG_BASE + 0x08 // Remote start address register 0
+#define RSAR1 ETH_REG_BASE + 0x09 // Remote start address register 0
+#define RBCR0 ETH_REG_BASE + 0x0A // Remote byte count register 0
+#define RBCR1 ETH_REG_BASE + 0x0B // Remote byte count register 1
+#define RCR ETH_REG_BASE + 0x0C // Receive configuration register
+ // Receive configuration register bits (write in page 0, read in page 2)
+ #define MON 0x20 // Monitor mode select bit
+ #define PRO 0x10 // Promiscuous mode select bit
+ #define AM 0x08 // Multicast packet accept bit
+ #define AB 0x04 // Broadcast packet accept bit
+ #define AR 0x02 // Runt packet accept bit
+ #define SEP 0x01 // Error packet accept bit
+#define TCR ETH_REG_BASE + 0x0D // Transmit configuration register
+ // Transmit configuration register bits
+ #define OFST 0x10 // Collision offset enable bit
+ #define ATD 0x08 // Auto transmit disable select bit
+ #define LB1 0x04 // Loopback mode select bit 1
+ #define LB0 0x02 // Loopback mode select bit 0
+ #define CRC 0x01 // CRC generation inhibit bit
+#define DCR ETH_REG_BASE + 0x0E // Data configuration register
+ // Data configuration register bits (write in page 0, read in page 2)
+ #define FT1 0x40 // FIFO threshold select bit 1
+ #define FT0 0x20 // FIFO threshold select bit 0
+ #define ARM 0x10 // Auto-initialise remote
+ #define LS 0x08 // Loopback select bit
+ #define LAS 0x04 // Set to 0 (pwrup = 1)
+ #define BOS 0x02 // Byte order select bit
+ #define WTS 0x01 // Word transfer select bit
+#define IMR ETH_REG_BASE + 0x0F // Interrupt mask register
+ // Interrupt mask register bits
+ // Each enable bit correspons with an interrupt flag in ISR
+
+// Page 1 read/write registers.
+#define PAR0 ETH_REG_BASE + 0x01 // Physical address register 0
+#define PAR1 ETH_REG_BASE + 0x02 // Physical address register 1
+#define PAR2 ETH_REG_BASE + 0x03 // Physical address register 2
+#define PAR3 ETH_REG_BASE + 0x04 // Physical address register 3
+#define PAR4 ETH_REG_BASE + 0x05 // Physical address register 4
+#define PAR5 ETH_REG_BASE + 0x06 // Physical address register 5
+#define CURR ETH_REG_BASE + 0x07 // Current receive buffer page
+#define MAR0 ETH_REG_BASE + 0x08
+#define MAR1 ETH_REG_BASE + 0x09
+#define MAR2 ETH_REG_BASE + 0x0A
+#define MAR3 ETH_REG_BASE + 0x0B
+#define MAR4 ETH_REG_BASE + 0x0C
+#define MAR5 ETH_REG_BASE + 0x0D
+#define MAR6 ETH_REG_BASE + 0x0E
+#define MAR7 ETH_REG_BASE + 0x0F
+
+// Page 2 read only registers.
+// Each previously defined in page 0 write only.
+//#define PSTART ETH_REG_BASE + 0x01
+//#define PSTOP ETH_REG_BASE + 0x02
+//#define TPSR ETH_REG_BASE + 0x04
+//#define RCR ETH_REG_BASE + 0x0C
+//#define TCR ETH_REG_BASE + 0x0D
+//#define DCR ETH_REG_BASE + 0x0E
+//#define IMR ETH_REG_BASE + 0x0F
+
+// Page 3 read/write registers.
+#define _9346CR ETH_REG_BASE + 0x01 // 9346 EEPROM command register
+ // 9346 EEPROM command register bits
+ #define EEM1 0x80 // RTL8019AS operating mode bit 1
+ #define EEM0 0x40 // RTL8019AS operating mode bit 0
+ #define EECS 0x08 // 9346 EEPROM chip select bit
+ #define EESK 0x04 // 9346 EEPROM serial clock bit
+ #define EEDI 0x02 // 9346 EEPROM data input bit
+ #define EEDO 0x01 // 9346 EEPROM data output bit
+#define BPAGE ETH_REG_BASE + 0x02
+#define CONFIG1 ETH_REG_BASE + 0x04 // RTL9019AS config register 1
+ // RTL9019AS config register 1 bits
+ #define IRQEN 0x80 // IRQ enable bit (WR protected)
+ #define IRQS2 0x40 // IRQ line select bit 2
+ #define IRQS1 0x20 // IRQ line select bit 1
+ #define IRQS0 0x10 // IRQ line select bit 0
+ #define IOS3 0x08 // I/O base address select bit 3
+ #define IOS2 0x04 // I/O base address select bit 2
+ #define IOS1 0x02 // I/O base address select bit 1
+ #define IOS0 0x01 // I/O base address select bit 0
+#define CONFIG2 ETH_REG_BASE + 0x05 //
+ // RTL9019AS config register 2 bits
+ #define PL1 0x80 // Network medium type select bit 1
+ #define PL0 0x40 // Network medium type select bit 0
+ #define BSELB 0x20 // Boot ROM disable (WR protected)
+ #define BS4 0x10 // Boot ROM configuration bit 4
+ #define BS3 0x08 // Boot ROM configuration bit 3
+ #define BS2 0x04 // Boot ROM configuration bit 2
+ #define BS1 0x02 // Boot ROM configuration bit 1
+ #define BS0 0x01 // Boot ROM configuration bit 0
+#define CONFIG3 ETH_REG_BASE + 0x06 // RTL9019AS config register 3
+ // RTL9019AS config register 3 bits
+ #define PNP 0x80 // Plug & play mode indicator bit
+ #define FUDUP 0x40 // Full duplex mode select bit
+ #define LEDS1 0x20 // LED output select bit 1
+ #define LEDS0 0x10 // LED output select bit 0
+ #define SLEEP 0x04 // Sleep mode select bit
+ #define PWRDN 0x02 // Power down mode select bit
+ #define ACTIVEB 0x01 // Inverse of bit 0, PNP active reg
+
+// Page 3 read only registers.
+#define CONFIG0 ETH_REG_BASE + 0x03 // RTL9019AS config register 0
+ // RTL9019AS config register 0 bits
+ #define VERID1 0x80 // RTL9019AS version ID bit 1 (R/W)
+ #define VERID0 0x40 // RTL9019AS version ID bit 0 (R/W)
+ #define AUI 0x20 // AUI input pin state bit
+ #define PNPJP 0x10 // PNP jumper pin state bit
+ #define JP 0x08 // JP input pin state bit
+ #define BNC 0x04 // Thinnet mode indication bit
+#define CSNSAV ETH_REG_BASE + 0x08
+#define INTR ETH_REG_BASE + 0x0B
+#define CONFIG4 ETH_REG_BASE + 0x0D
+
+// Page 3 write only registers.
+#define TEST ETH_REG_BASE + 0x07
+#define HLTCLK ETH_REG_BASE + 0x09
+#define FMWP ETH_REG_BASE + 0x0C
+
+
+// Bits del byte de status del frame recibido
+#define RXSOK 0x01 /* Received a good packet */
+#define RXSCRC 0x02 /* CRC error */
+#define RXSFAE 0x04 /* frame alignment error */
+#define RXSFO 0x08 /* FIFO overrun */
+#define RXSMPA 0x10 /* missed pkt */
+#define RXSPHY 0x20 /* physical/multicast address */
+#define RXSDIS 0x40 /* receiver disable. set in monitor mode */
+#define RXSDEF 0x80 /* deferring */
+
+
+bit etherdev_init(void);
+void etherdev_send(void);
+unsigned int etherdev_read(void);
+
+#endif
projects / z.facultad / 66.09 / etherled.git / blobdiff