Faltó reemplazar un petherled por EPL =)

[z.facultad/66.09/etherled.git] / src / dp8390.h

diff --git a/src/dp8390.h b/src/dp8390.h
index 0d2fa399d251a61259f65d933ea25db56a3ed422..dfd19d689f7390d5daa3a0908419d32759b5df5d 100644 (file)
--- a/src/dp8390.h
+++ b/src/dp8390.h
@@ -14,7 +14,7 @@
 #define ADDR_PORT_MASK  0x1F    // Máscara de direcciones (para no cambiar
                                 // bits que no se usan)
 #ifdef SDCC
 #define ADDR_PORT_MASK  0x1F    // Máscara de direcciones (para no cambiar
                                 // bits que no se usan)
 #ifdef SDCC

-sbit at 0xB2 IOW;   // ISA slot pin B13, RTL8019AS pin 30, active low
+sbit at 0xB4 IOW;   // ISA slot pin B13, RTL8019AS pin 30, active low

 sbit at 0xB5 IOR;   // ISA slot pin B14, RTL8019AS pin 29, active low
 sbit at 0xB2 NICE;  // A7, usado para activar placa de red
 #else
 sbit at 0xB5 IOR;   // ISA slot pin B14, RTL8019AS pin 29, active low
 sbit at 0xB2 NICE;  // A7, usado para activar placa de red
 #else


@@ -24,15 +24,15 @@ sbit IOR = CTRL_PORT^5;     // ISA slot pin B14, RTL8019AS pin 29, active low
 sbit NICE = CTRL_PORT^2;    // A7, usado para activar placa de red
 #endif
 
 sbit NICE = CTRL_PORT^2;    // A7, usado para activar placa de red
 #endif
 

-// Configuración de paǵinas de buffers
-#define TX_PAGE_START  0x40      // 0x4000 Tx buffer:  6 * 256 = 1536 bytes
-#define RX_PAGE_START  0x46      // 0x4600 Rx buffer: 26 * 256 = 6656 bytes
-#define RX_PAGE_STOP   0x60      // 0x6000
-

 // Límites de tamaño de paquete
 #define MIN_PACKET_LEN 60u  // Mínimo permitido por 802.3
 #define MAX_PACKET_LEN 128u // Mínimo permitido por nuestra escasa memoria =)
 
 // Límites de tamaño de paquete
 #define MIN_PACKET_LEN 60u  // Mínimo permitido por 802.3
 #define MAX_PACKET_LEN 128u // Mínimo permitido por nuestra escasa memoria =)
 

+// Configuración de paǵinas de buffers
+#define TX_PAGE_START  0x40 // 0x4000 Tx buffer: 256 bytes (usamos 128)
+#define RX_PAGE_START  0x41 // 0x4600 Rx buffer: 31 * 256 = 7936 bytes
+#define RX_PAGE_STOP   0x60 // 0x6000
+

 // Register base address
 #define REG_BASE 0x0000 // Hardwired to 0x0300
 
 // Register base address
 #define REG_BASE 0x0000 // Hardwired to 0x0300
 


@@ -49,15 +49,15 @@ sbit NICE = CTRL_PORT^2;    // A7, usado para activar placa de red
     #define STP      0x01                  // Stop bit transceiver ctrl
     // Shortcuts
     #define PAGE0    0x00                  // Page 0
     #define STP      0x01                  // Stop bit transceiver ctrl
     // Shortcuts
     #define PAGE0    0x00                  // Page 0

-    #define PAGE1    0x40                  // Page 1
-    #define PAGE2    0x80                  // Page 2
-    #define PAGE3    0xC0                  // Page 3 (Reserved!)
-    #define ABORT    0x20                  // Abort/Complete DMA
-    #define READ     0x0A                  // Remote Read (RD0 | STA)
-    #define WRITE    0x12                  // Remote Write (RD1 | STA)
-    #define SENDPKT  0x1A                  // Send Packet (RD0 | RD1 | STA)
-    #define STOP     0x21                  // STP | ABORT
-    #define START    0x22                  // STA | ABORT
+    #define PAGE1    PS0                   // Page 1
+    #define PAGE2    PS1                   // Page 2
+    #define PAGE3    (PS0 | PS1)           // Page 3 (Reserved!)
+    #define ABORT    RD2                   // Abort/Complete DMA
+    #define READ     (RD0 | STA)           // Remote Read
+    #define WRITE    (RD1 | STA)           // Remote Write
+    #define SENDPKT  (RD0 | RD1 | STA)     // Send Packet
+    #define STOP     (ABORT | STP)         // Para la placa de red
+    #define START    (ABORT | STA)         // Inicia la placa de red

 
 #define RDMA         0x10                  // Remote DMA port
 #define RESET        0x18                  // Reset port
 
 #define RDMA         0x10                  // Remote DMA port
 #define RESET        0x18                  // Reset port


@@ -120,9 +120,9 @@ sbit NICE = CTRL_PORT^2;    // A7, usado para activar placa de red
     #define CRC      0x01                  // CRC generation inhibit bit
     // Shortcuts
     #define MODE0    0x00                  // Loopback mode 0
     #define CRC      0x01                  // CRC generation inhibit bit
     // Shortcuts
     #define MODE0    0x00                  // Loopback mode 0

-    #define MODE1    0x02                  // Loopback mode 1
-    #define MODE2    0x04                  // Loopback mode 2
-    #define MODE3    0x06                  // Loopback mode 3
+    #define MODE1    LB0                   // Loopback mode 1
+    #define MODE2    LB1                   // Loopback mode 2
+    #define MODE3    (LB0 | LB1)           // Loopback mode 3

 #define DCR          REG_BASE + 0x0E   // Data configuration register
     // Data configuration register bits (write in page 0, read in page 2)
     #define FT1      0x40                  // FIFO threshold select bit 1
 #define DCR          REG_BASE + 0x0E   // Data configuration register
     // Data configuration register bits (write in page 0, read in page 2)
     #define FT1      0x40                  // FIFO threshold select bit 1


@@ -137,6 +137,7 @@ sbit NICE = CTRL_PORT^2;    // A7, usado para activar placa de red
     // Each enable bit correspons with an interrupt flag in ISR
 
 // Page 1 read/write registers.
     // Each enable bit correspons with an interrupt flag in ISR
 
 // Page 1 read/write registers.

+#define PAR_BASE     REG_BASE + 0x01   // Physical address register base address

 #define PAR0         REG_BASE + 0x01   // Physical address register 0
 #define PAR1         REG_BASE + 0x02   // Physical address register 1
 #define PAR2         REG_BASE + 0x03   // Physical address register 2
 #define PAR0         REG_BASE + 0x01   // Physical address register 0
 #define PAR1         REG_BASE + 0x02   // Physical address register 1
 #define PAR2         REG_BASE + 0x03   // Physical address register 2