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[z.facultad/66.09/etherled.git] / pruebas / keil / red_test_anda / etherdev.h

diff --git a/pruebas/keil/red_test_anda/etherdev.h b/pruebas/keil/red_test_anda/etherdev.h
index 2f0c298881d58c6a290bf666a7750a3bf95a2f03..32dbb57357e38d0da8459b394f70c754aaa49a00 100644 (file)
--- a/pruebas/keil/red_test_anda/etherdev.h
+++ b/pruebas/keil/red_test_anda/etherdev.h
@@ -3,7 +3,7 @@
 #ifndef ETHERDEV_H
 #define ETHERDEV_H
 
 #ifndef ETHERDEV_H
 #define ETHERDEV_H
 

-#include "REG51.h"
+#include "reg51.h"

 
 extern unsigned char uip_buf[80];
 extern unsigned int uip_len;
 
 extern unsigned char uip_buf[80];
 extern unsigned int uip_len;


@@ -11,10 +11,16 @@ extern unsigned int uip_len;
 
 #define ETH_DATA_PORT P2     // Adjust this to suit hardware.
 #define ETH_ADDR_PORT P1     // Adjust this to suit hardware.
 
 #define ETH_DATA_PORT P2     // Adjust this to suit hardware.
 #define ETH_ADDR_PORT P1     // Adjust this to suit hardware.

-#define ETH_CTRL_PORT P3     // Adjust this to suit hardware.
-sbit IOW = ETH_CTRL_PORT^4;  // ISA slot pin B13, RTL8019AS pin 30, active low
-sbit IOR = ETH_CTRL_PORT^5;  // ISA slot pin B14, RTL8019AS pin 29, active low
-sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red
+#ifdef SDCC
+sbit at 0xB4 IOW;   // ISA slot pin B13, RTL8019AS pin 30, active low
+sbit at 0xB5 IOR;   // ISA slot pin B14, RTL8019AS pin 29, active low
+sbit at 0xB2 NICE;  // A7, usado para activar placa de red
+#else
+#define CTRL_PORT       P3  // Adjust this to suit hardware.
+sbit IOW = CTRL_PORT^4;     // ISA slot pin B13, RTL8019AS pin 30, active low
+sbit IOR = CTRL_PORT^5;     // ISA slot pin B14, RTL8019AS pin 29, active low
+sbit NICE = CTRL_PORT^2;    // A7, usado para activar placa de red
+#endif

 
 
 // Register base address
 
 
 // Register base address


@@ -31,6 +37,15 @@ sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red
     #define TXP      0x04                  // Transmit packet bit
     #define STA      0x02                  // Start bit (a flag only)
     #define STP      0x01                  // Stop bit transceiver ctrl
     #define TXP      0x04                  // Transmit packet bit
     #define STA      0x02                  // Start bit (a flag only)
     #define STP      0x01                  // Stop bit transceiver ctrl

+    // Shortcuts
+    #define PAGE0    0x00                  // Page 0
+    #define PAGE1    0x40                  // Page 1
+    #define PAGE2    0x80                  // Page 2
+    #define PAGE3    0xC0                  // Page 3 (Reserved!)
+    #define ABORT    0x20                  // Abort/Complete DMA
+    #define READ     0x08                  // Remote Read
+    #define WRITE    0x10                  // Remote Write
+    #define SENDPKT  0x18                  // Send Packet Command

 #define RDMA         0x10                  // Remote DMA port
 #define RESET        0x18                  // Reset port
 
 #define RDMA         0x10                  // Remote DMA port
 #define RESET        0x18                  // Reset port
 


@@ -87,6 +102,11 @@ sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red
     #define LB1      0x04                  // Loopback mode select bit 1
     #define LB0      0x02                  // Loopback mode select bit 0
     #define CRC      0x01                  // CRC generation inhibit bit
     #define LB1      0x04                  // Loopback mode select bit 1
     #define LB0      0x02                  // Loopback mode select bit 0
     #define CRC      0x01                  // CRC generation inhibit bit

+    // Shortcuts
+    #define MODE0    0x00                  // Loopback mode 0
+    #define MODE1    0x02                  // Loopback mode 1
+    #define MODE2    0x04                  // Loopback mode 2
+    #define MODE3    0x06                  // Loopback mode 3

 #define DCR          ETH_REG_BASE + 0x0E   // Data configuration register
     // Data configuration register bits (write in page 0, read in page 2)
     #define FT1      0x40                  // FIFO threshold select bit 1
 #define DCR          ETH_REG_BASE + 0x0E   // Data configuration register
     // Data configuration register bits (write in page 0, read in page 2)
     #define FT1      0x40                  // FIFO threshold select bit 1


@@ -197,7 +217,7 @@ sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red
 #define RXSDEF     0x80    /* deferring */
 
 
 #define RXSDEF     0x80    /* deferring */
 
 

-bit etherdev_init(void);
+bool etherdev_init(void);

 void etherdev_send(void);
 unsigned int etherdev_read(void);
 
 void etherdev_send(void);
 unsigned int etherdev_read(void);