X-Git-Url: https://git.llucax.com/z.facultad/66.09/etherled.git/blobdiff_plain/3be9796df73e200ae3778316a3ac696370731289..0052faf6d85ec776823a1a33efc8d911b4b4e2f6:/pruebas/keil/red_test_anda/etherdev.c diff --git a/pruebas/keil/red_test_anda/etherdev.c b/pruebas/keil/red_test_anda/etherdev.c index d3b1a5a..93abcbf 100644 --- a/pruebas/keil/red_test_anda/etherdev.c +++ b/pruebas/keil/red_test_anda/etherdev.c @@ -1,11 +1,17 @@ // vim: set et sw=4 sts=4 : +#include "types.h" #include "etherdev.h" void sleep(unsigned char); -static xdata leds1 _at_ 0x0080; -static xdata leds2 _at_ 0x00c0; +#ifdef SDCC +static xdata at 0x0080 byte leds1; +static xdata at 0x00c0 byte leds2; +#else +static byte xdata leds1 _at_ 0x0080; +static byte xdata leds2 _at_ 0x00c0; +#endif unsigned char uip_buf[80] = { @@ -56,9 +62,6 @@ static void etherdev_reg_write(unsigned char reg, unsigned char wr_data) IOW = 1; NICE = 1; - // Set register data port as input again. - ETH_DATA_PORT = ETH_DATA_PORT_MASK; - return; } @@ -71,6 +74,9 @@ static unsigned char etherdev_reg_read(unsigned char reg) ETH_ADDR_PORT &= ~ETH_ADDR_PORT_MASK; ETH_ADDR_PORT |= reg; + // Set register data port as input. + ETH_DATA_PORT = ETH_DATA_PORT_MASK; + // Enable register data output from RTL8019AS. NICE = 0; IOR = 0; @@ -94,7 +100,7 @@ static unsigned char etherdev_reg_read(unsigned char reg) Refer to National Semiconductor DP8390 App Note 874, July 1993. */ -bit etherdev_init(void) +bool etherdev_init(void) { // Set IOR & IOW as they're active low. IOR = 1; @@ -120,7 +126,7 @@ bit etherdev_init(void) } // Stop RTL8019AS, select page 0 and abort DMA operation. - etherdev_reg_write(CR, RD2 | STP); + etherdev_reg_write(CR, ABORT | STP); // Initialise data configuration register. // FIFO threshold 8 bytes, no loopback, don't use auto send packet. @@ -134,20 +140,20 @@ bit etherdev_init(void) etherdev_reg_write(RCR, MON); // Initialise transmit configuration register to loopback internally. - etherdev_reg_write(TCR, LB0); + etherdev_reg_write(TCR, MODE1); // Clear interrupt status register bits by writing 1 to each. etherdev_reg_write(ISR, 0xFF); // Mask all interrupts in mask register. etherdev_reg_write(IMR, 0x00); - + // Obtengo MAC de la placa etherdev_reg_write(RBCR0, 0x0c); // Vamos a leer 12 bytes (2 x 6) etherdev_reg_write(RBCR1, 0x00); etherdev_reg_write(RSAR0, 0x00); // En la dirección 0x0000 etherdev_reg_write(RSAR1, 0x00); - etherdev_reg_write(CR, RD0 | STA); // Comienza lectura + etherdev_reg_write(CR, READ | STA); // Comienza lectura uip_buf[6] = etherdev_reg_read(RDMA); etherdev_reg_read(RDMA); // Ignoramos porque viene como un word uip_buf[7] = etherdev_reg_read(RDMA); @@ -165,7 +171,7 @@ bit etherdev_init(void) while(!(etherdev_reg_read(ISR) & RDC)) continue; // Abort/ complete DMA operation. - etherdev_reg_write(CR, RD2 | STP); + etherdev_reg_write(CR, ABORT | STP); // Limpia ISR etherdev_reg_write(ISR, RDC); @@ -183,27 +189,27 @@ bit etherdev_init(void) etherdev_reg_write(PSTOP, ETH_RX_PAGE_STOP); // Select RTL8019AS register page 1. - etherdev_reg_write(CR, RD2 | PS0 | STP); + etherdev_reg_write(CR, ABORT | PAGE1 | STP); // Initialise current packet receive buffer page pointer etherdev_reg_write(CURR, ETH_RX_PAGE_START + 1); // Set physical address - etherdev_reg_write(PAR0, uip_buf[0]); - etherdev_reg_write(PAR1, uip_buf[0]); - etherdev_reg_write(PAR2, uip_buf[0]); - etherdev_reg_write(PAR3, uip_buf[0]); - etherdev_reg_write(PAR4, uip_buf[0]); - etherdev_reg_write(PAR5, uip_buf[0]); + etherdev_reg_write(PAR0, uip_buf[6]); + etherdev_reg_write(PAR1, uip_buf[7]); + etherdev_reg_write(PAR2, uip_buf[8]); + etherdev_reg_write(PAR3, uip_buf[9]); + etherdev_reg_write(PAR4, uip_buf[10]); + etherdev_reg_write(PAR5, uip_buf[11]); // Select RTL8019AS register page 0 and abort DMA operation. - etherdev_reg_write(CR, RD2 | STP); + etherdev_reg_write(CR, ABORT | STP); // Restart RTL8019AS. - etherdev_reg_write(CR, RD2 | STA); + etherdev_reg_write(CR, ABORT | STA); // Initialise transmit configuration register for normal operation. - etherdev_reg_write(TCR, 0x00); + etherdev_reg_write(TCR, MODE0); // Receive configuration register to accept broadcast packets. etherdev_reg_write(RCR, AB); @@ -227,7 +233,7 @@ void etherdev_send(void) // Setup for DMA transfer from uip_buf & uip_appdata buffers to RTL8019AS. // Select RTL8019AS register page 0 and abort DMA operation. - etherdev_reg_write(CR, RD2 | STA); + etherdev_reg_write(CR, ABORT | STA); // Wait until pending transmit operation completes. while(etherdev_reg_read(CR) & TXP) continue; @@ -241,7 +247,7 @@ void etherdev_send(void) etherdev_reg_write(RBCR1, (unsigned char)(uip_len >> 8)); // Initiate DMA transfer of uip_buf & uip_appdata buffers to RTL8019AS. - etherdev_reg_write(CR, RD1 | STA); + etherdev_reg_write(CR, WRITE | STA); // DMA transfer packet from uip_buf & uip_appdata to RTL8019AS local // transmit buffer memory. @@ -257,7 +263,7 @@ void etherdev_send(void) etherdev_reg_write(ISR, RDC); // Abort/ complete DMA operation. - etherdev_reg_write(CR, RD2 | STA); + etherdev_reg_write(CR, ABORT | STA); // Set transmit page start to indicate packet start. etherdev_reg_write(TPSR, ETH_TX_PAGE_START); @@ -273,7 +279,7 @@ void etherdev_send(void) etherdev_reg_write(TBCR1, (unsigned char)(uip_len >> 8)); // Issue command for RTL8019AS to transmit packet from it's local buffer. - etherdev_reg_write(CR, RD2 | TXP | STA); + etherdev_reg_write(CR, ABORT | TXP | STA); return; } @@ -288,7 +294,7 @@ static void etherdev_reset() // data it contains is uncorrupted, or will cause us grief. // Stop RTL8019AS and abort DMA operation. - etherdev_reg_write(CR, RD2 | STP); + etherdev_reg_write(CR, ABORT | STP); // Wait for controller to halt after any current tx completes. while(!(etherdev_reg_read(ISR) & RST)) continue; @@ -309,10 +315,10 @@ static void etherdev_reset() } // Set transmit configuration register to loopback internally. - etherdev_reg_write(TCR, LB0); + etherdev_reg_write(TCR, MODE1); // Restart the RTL8019AS. - etherdev_reg_write(CR, RD2 | STA); + etherdev_reg_write(CR, ABORT | STA); // Re-initialise last receive buffer read pointer. etherdev_reg_write(BNRY, ETH_RX_PAGE_START); @@ -330,12 +336,12 @@ static void etherdev_reset() etherdev_reg_write(ISR, PRX | OVW); // Re-itialise transmit configuration reg for normal operation. - etherdev_reg_write(TCR, 0x00); + etherdev_reg_write(TCR, MODE0); if(retransmit) { // Retransmit packet in RTL8019AS local tx buffer. - etherdev_reg_write(CR, RD2 | TXP | STA); + etherdev_reg_write(CR, ABORT | TXP | STA); } } @@ -417,7 +423,7 @@ unsigned int etherdev_read(void) etherdev_reg_write(ISR, RDC); // Initiate DMA transfer of packet header. - etherdev_reg_write(CR, RD0 | STA); + etherdev_reg_write(CR, READ | STA); // Packet status. status = etherdev_reg_read(RDMA); @@ -434,7 +440,7 @@ unsigned int etherdev_read(void) while(!(etherdev_reg_read(ISR) & RDC)) continue; // Abort/ complete DMA operation. - etherdev_reg_write(CR, RD2 | STA); + etherdev_reg_write(CR, ABORT | STA); // Limpia ISR etherdev_reg_write(ISR, RDC); @@ -468,7 +474,7 @@ unsigned int etherdev_read(void) etherdev_reg_write(RBCR1, (unsigned char)(len >> 8)); // Initiate DMA transfer of packet data. - etherdev_reg_write(CR, RD0 | STA); + etherdev_reg_write(CR, READ | STA); // Read packet data directly into uip_buf. uip_len = len; @@ -485,7 +491,7 @@ unsigned int etherdev_read(void) while(!(etherdev_reg_read(ISR) & RDC)) continue; // Abort/ complete DMA operation. - etherdev_reg_write(CR, RD2 | STA); + etherdev_reg_write(CR, ABORT | STA); // Clear remote DMA complete interrupt status register bit. etherdev_reg_write(ISR, RDC);