X-Git-Url: https://git.llucax.com/z.facultad/66.09/etherled.git/blobdiff_plain/b28157390ed405302bd3394b0ea139d1b5d70432..c0e5d185c08cc8c099e9a3a93e62d422ca0e7ebf:/pruebas/keil/red_test_anda/etherdev.h diff --git a/pruebas/keil/red_test_anda/etherdev.h b/pruebas/keil/red_test_anda/etherdev.h index 1770cc0..32dbb57 100644 --- a/pruebas/keil/red_test_anda/etherdev.h +++ b/pruebas/keil/red_test_anda/etherdev.h @@ -1,120 +1,27 @@ -/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ» - º TITLE: RTL8019AS ethernet routines for 8051 and º - º Keil C51 v7.00 port of Adam Dunkels' uIP v0.9 º - º FILENAME: etherdev.h º - º REVISION: VER 0.0 º - º REV.DATE: 21-01-05 º - º ARCHIVE: º - º AUTHOR: Copyright (c) 2005, Murray R. Van Luyn. º - ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */ - -/* ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿ - ³ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS ³ - ³ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ³ - ³ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ³ - ³ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY ³ - ³ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ³ - ³ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ³ - ³ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ³ - ³ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ³ - ³ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ³ - ³ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ³ - ³ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ³ - ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ */ - +// vim: set et sw=4 sts=4 : #ifndef ETHERDEV_H #define ETHERDEV_H -#include "REG51.h" +#include "reg51.h" extern unsigned char uip_buf[80]; extern unsigned int uip_len; -/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ» - º º - º Public defines. º - º º - ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */ -// Change ETH_CPU_XTAL to match hardware -#define ETH_CPU_XTAL 24000000 // 8051 crystal freq in Hz - - -/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ» - º º - º ISA Expansion slot signal to 8051 port mapping. º - º º - ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */ #define ETH_DATA_PORT P2 // Adjust this to suit hardware. #define ETH_ADDR_PORT P1 // Adjust this to suit hardware. -#define ETH_CTRL_PORT P3 // Adjust this to suit hardware. -sbit IOW = ETH_CTRL_PORT^4; // ISA slot pin B13, RTL8019AS pin 30, active low -sbit IOR = ETH_CTRL_PORT^5; // ISA slot pin B14, RTL8019AS pin 29, active low -sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red - - -/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ» - º º - º Required additional ISA slot wiring. º - º º - ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */ -// SD0 ETH_DATA_PORT^0 // ISA slot pin A9, RTL8019AS pin 36 -// SD1 ETH_DATA_PORT^1 // ISA slot pin A8, RTL8019AS pin 37 -// SD2 ETH_DATA_PORT^2 // ISA slot pin A7, RTL8019AS pin 38 -// SD3 ETH_DATA_PORT^3 // ISA slot pin A6, RTL8019AS pin 39 -// SD4 ETH_DATA_PORT^4 // ISA slot pin A5, RTL8019AS pin 40 -// SD5 ETH_DATA_PORT^5 // ISA slot pin A4, RTL8019AS pin 41 -// SD6 ETH_DATA_PORT^6 // ISA slot pin A3, RTL8019AS pin 42 -// SD7 ETH_DATA_PORT^7 // ISA slot pin A2, RTL8019AS pin 43 -// SA0 ETH_ADDR_PORT^0 // ISA slot pin A31, RTL8019AS pin 5 -// SA1 ETH_ADDR_PORT^1 // ISA slot pin A30, RTL8019AS pin 7 -// SA2 ETH_ADDR_PORT^2 // ISA slot pin A29, RTL8019AS pin 8 -// SA3 ETH_ADDR_PORT^3 // ISA slot pin A28, RTL8019AS pin 9 -// SA4 ETH_ADDR_PORT^4 // ISA slot pin A27, RTL8019AS pin 10 -// SA5 GND // ISA slot pin A26, RTL8019AS pin 11 -// SA6 GND // ISA slot pin A25, RTL8019AS pin 12 -// SA7 GND // ISA slot pin A24, RTL8019AS pin 13 -// SA8 +5V // ISA slot pin A23, RTL8019AS pin 15 -// SA9 +5V // ISA slot pin A22, RTL8019AS pin 16 -// SA10 GND // ISA slot pin A21, RTL8019AS pin 18 -// SA11 GND // ISA slot pin A20, RTL8019AS pin 19 -// SA12 GND // ISA slot pin A19, RTL8019AS pin 20 -// SA13 GND // ISA slot pin A18, RTL8019AS pin 21 -// SA14 GND // ISA slot pin A17, RTL8019AS pin 22 -// SA15 GND // ISA slot pin A16, RTL8019AS pin 23 -// SA16 GND // ISA slot pin A15, RTL8019AS pin 24 -// SA17 GND // ISA slot pin A14, RTL8019AS pin 25 -// SA18 GND // ISA slot pin A13, RTL8019AS pin 26 -// SA19 GND // ISA slot pin A12, RTL8019AS pin 27 -// AEN GND // ISA slot pin A11, RTL8019AS pin 34 -// SMEMW +5V // ISA slot pin B11, RTL8019AS pin 32 -// SMEMR +5V // ISA slot pin B12, RTL8019AS pin 31 -// GND GND // ISA slot pin B1 -// +5VDC +5V // ISA slot pin B3 -// GND GND // ISA slot pin B31 -// +5VDC +5V // ISA slot pin B29 -// RESET ? // ISA slot pin B2, active high reset input - - -/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ» - º º - º ISA 16 bit expansion slot edge connector. º - º º - ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */ - -// ³ ÚÄÄÄÄÄ¿ ³ -// ³C18 C1³ ³A31 Component side A1³ -// ÔÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ; ÔÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ; -// D18 D1 B31 Solder side B1 - - +#ifdef SDCC +sbit at 0xB4 IOW; // ISA slot pin B13, RTL8019AS pin 30, active low +sbit at 0xB5 IOR; // ISA slot pin B14, RTL8019AS pin 29, active low +sbit at 0xB2 NICE; // A7, usado para activar placa de red +#else +#define CTRL_PORT P3 // Adjust this to suit hardware. +sbit IOW = CTRL_PORT^4; // ISA slot pin B13, RTL8019AS pin 30, active low +sbit IOR = CTRL_PORT^5; // ISA slot pin B14, RTL8019AS pin 29, active low +sbit NICE = CTRL_PORT^2; // A7, usado para activar placa de red +#endif -/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ» - º º - º RTL8019AS Register defines. º - º º - ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */ // Register base address #define ETH_REG_BASE 0x0000 // Hardwired to 0x0300 @@ -130,6 +37,15 @@ sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red #define TXP 0x04 // Transmit packet bit #define STA 0x02 // Start bit (a flag only) #define STP 0x01 // Stop bit transceiver ctrl + // Shortcuts + #define PAGE0 0x00 // Page 0 + #define PAGE1 0x40 // Page 1 + #define PAGE2 0x80 // Page 2 + #define PAGE3 0xC0 // Page 3 (Reserved!) + #define ABORT 0x20 // Abort/Complete DMA + #define READ 0x08 // Remote Read + #define WRITE 0x10 // Remote Write + #define SENDPKT 0x18 // Send Packet Command #define RDMA 0x10 // Remote DMA port #define RESET 0x18 // Reset port @@ -186,6 +102,11 @@ sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red #define LB1 0x04 // Loopback mode select bit 1 #define LB0 0x02 // Loopback mode select bit 0 #define CRC 0x01 // CRC generation inhibit bit + // Shortcuts + #define MODE0 0x00 // Loopback mode 0 + #define MODE1 0x02 // Loopback mode 1 + #define MODE2 0x04 // Loopback mode 2 + #define MODE3 0x06 // Loopback mode 3 #define DCR ETH_REG_BASE + 0x0E // Data configuration register // Data configuration register bits (write in page 0, read in page 2) #define FT1 0x40 // FIFO threshold select bit 1 @@ -285,12 +206,18 @@ sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red #define FMWP ETH_REG_BASE + 0x0C +// Bits del byte de status del frame recibido +#define RXSOK 0x01 /* Received a good packet */ +#define RXSCRC 0x02 /* CRC error */ +#define RXSFAE 0x04 /* frame alignment error */ +#define RXSFO 0x08 /* FIFO overrun */ +#define RXSMPA 0x10 /* missed pkt */ +#define RXSPHY 0x20 /* physical/multicast address */ +#define RXSDIS 0x40 /* receiver disable. set in monitor mode */ +#define RXSDEF 0x80 /* deferring */ -/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ» - º Public Function Prototypes º - ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */ -bit etherdev_init(void); +bool etherdev_init(void); void etherdev_send(void); unsigned int etherdev_read(void);