Pongo svn:ignore un poco más poderoso y agrego un par de archivos que estaban

perdidos y actualizo proyecto de Keil.

diff --git a/src/etherled.Uv2 b/src/etherled.Uv2
index f9bea75ac020ae3d9cfee67cca249c30832954a1..a07d2cb83ca222d9a522af079a167c31d19f7544 100644 (file)
--- a/src/etherled.Uv2
+++ b/src/etherled.Uv2
@@ -19,6 +19,7 @@ File 2,1,<.\main.c><main.c> 0x0
 File 2,5,<.\reg51.h><reg51.h> 0x0 \r
 File 2,2,<.\startup.a51><startup.a51> 0x0 \r
 File 2,5,<.\types.h><types.h> 0x0 \r
 File 2,5,<.\reg51.h><reg51.h> 0x0 \r
 File 2,2,<.\startup.a51><startup.a51> 0x0 \r
 File 2,5,<.\types.h><types.h> 0x0 \r

+File 2,5,<.\reg51keil.h><reg51keil.h> 0x0 \r

 \r
 \r
 Options 1,0,0  // Target 'etherled'\r
 \r
 \r
 Options 1,0,0  // Target 'etherled'\r


@@ -45,7 +46,7 @@ Options 1,0,0  // Target 'etherled'
  EnvLib ()\r
  EnvReg (ÿAtmel\)\r
  OrgReg (ÿAtmel\)\r
  EnvLib ()\r
  EnvReg (ÿAtmel\)\r
  OrgReg (ÿAtmel\)\r

- TgStat=25\r
+ TgStat=27\r

  OutDir (.\)\r
  OutName (etherled)\r
  GenApp=1\r
  OutDir (.\)\r
  OutName (etherled)\r
  GenApp=1\r


@@ -71,7 +72,7 @@ Options 1,0,0  // Target 'etherled'
  XT51FL=0\r
  CBANKS5=0\r
  XBANKS5=0\r
  XT51FL=0\r
  CBANKS5=0\r
  XBANKS5=0\r

- RCB51 { 0,0,0,0,0,0,0,1,0 }\r
+ RCB51 { 0,0,0,0,0,255,255,0,0 }\r

  RXB51 { 0,0,0,0,0,0,0,0,0 }\r
  OCM51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
  OCR51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
  RXB51 { 0,0,0,0,0,0,0,0,0 }\r
  OCM51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
  OCR51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r

diff --git a/src/reg51.h b/src/reg51.h
index 7b95f315111d6116fb0e601bd0fe8cb22f07f4b1..9f08bd6437c34ee109059f2ceddae0cb71fb1311 100644 (file)
--- a/src/reg51.h
+++ b/src/reg51.h
@@ -2,9 +2,9 @@
 #define _REG51_H_
 
 #ifdef SDCC
 #define _REG51_H_
 
 #ifdef SDCC

-#      include "reg51sdcc.h"
+#   include "reg51sdcc.h"

 #else
 #else

-#      include "reg51keil.h"
+#   include "reg51keil.h"

 #endif
 
 #endif /* _REG51_H_ */
 #endif
 
 #endif /* _REG51_H_ */

diff --git a/src/reg51keil.h b/src/reg51keil.h
new file mode 100644 (file)
index 0000000..ed182bf
--- /dev/null
+++ b/src/reg51keil.h
@@ -0,0 +1,82 @@
+#ifndef _REG51KEIL_H_
+#define _REG51KEIL_H_
+
+/*  BYTE Register  */
+sfr P0   = 0x80;
+sfr P1   = 0x90;
+sfr P2   = 0xA0;
+sfr P3   = 0xB0;
+sfr PSW  = 0xD0;
+sfr ACC  = 0xE0;
+sfr B    = 0xF0;
+sfr SP   = 0x81;
+sfr DPL  = 0x82;
+sfr DPH  = 0x83;
+sfr PCON = 0x87;
+sfr TCON = 0x88;
+sfr TMOD = 0x89;
+sfr TL0  = 0x8A;
+sfr TL1  = 0x8B;
+sfr TH0  = 0x8C;
+sfr TH1  = 0x8D;
+sfr IE   = 0xA8;
+sfr IP   = 0xB8;
+sfr SCON = 0x98;
+sfr SBUF = 0x99;
+
+/*  BIT Register  */
+/*  PSW   */
+sbit CY   = 0xD7;
+sbit AC   = 0xD6;
+sbit F0   = 0xD5;
+sbit RS1  = 0xD4;
+sbit RS0  = 0xD3;
+sbit OV   = 0xD2;
+sbit P    = 0xD0;
+
+/*  TCON  */
+sbit TF1  = 0x8F;
+sbit TR1  = 0x8E;
+sbit TF0  = 0x8D;
+sbit TR0  = 0x8C;
+sbit IE1  = 0x8B;
+sbit IT1  = 0x8A;
+sbit IE0  = 0x89;
+sbit IT0  = 0x88;
+
+/*  IE   */
+sbit EA   = 0xAF;
+sbit ES   = 0xAC;
+sbit ET1  = 0xAB;
+sbit EX1  = 0xAA;
+sbit ET0  = 0xA9;
+sbit EX0  = 0xA8;
+
+/*  IP   */ 
+sbit PS   = 0xBC;
+sbit PT1  = 0xBB;
+sbit PX1  = 0xBA;
+sbit PT0  = 0xB9;
+sbit PX0  = 0xB8;
+
+/*  P3  */
+sbit RD   = 0xB7;
+sbit WR   = 0xB6;
+sbit T1   = 0xB5;
+sbit T0   = 0xB4;
+sbit INT1 = 0xB3;
+sbit INT0 = 0xB2;
+sbit TXD  = 0xB1;
+sbit RXD  = 0xB0;
+
+/*  SCON  */
+sbit SM0  = 0x9F;
+sbit SM1  = 0x9E;
+sbit SM2  = 0x9D;
+sbit REN  = 0x9C;
+sbit TB8  = 0x9B;
+sbit RB8  = 0x9A;
+sbit TI   = 0x99;
+sbit RI   = 0x98;
+
+#endif /* _REG51KEIL_H_ */

diff --git a/src/reg51sdcc.h b/src/reg51sdcc.h
new file mode 100644 (file)
index 0000000..ca1bbaf
--- /dev/null
+++ b/src/reg51sdcc.h
@@ -0,0 +1,82 @@
+#ifndef _REG51SDCC_H_
+#define _REG51SDCC_H_
+
+/*  BYTE Register  */
+sfr at 0x80 P0;
+sfr at 0x90 P1;
+sfr at 0xA0 P2;
+sfr at 0xB0 P3;
+sfr at 0xD0 PSW;
+sfr at 0xE0 ACC;
+sfr at 0xF0 B;
+sfr at 0x81 SP;
+sfr at 0x82 DPL;
+sfr at 0x83 DPH;
+sfr at 0x87 PCON;
+sfr at 0x88 TCON;
+sfr at 0x89 TMOD;
+sfr at 0x8A TL0;
+sfr at 0x8B TL1;
+sfr at 0x8C TH0;
+sfr at 0x8D TH1;
+sfr at 0xA8 IE;
+sfr at 0xB8 IP;
+sfr at 0x98 SCON;
+sfr at 0x99 SBUF;
+
+/*  BIT Register  */
+/*  PSW   */
+sbit at 0xD7 CY;
+sbit at 0xD6 AC;
+sbit at 0xD5 F0;
+sbit at 0xD4 RS1;
+sbit at 0xD3 RS0;
+sbit at 0xD2 OV;
+sbit at 0xD0 P;
+
+/*  TCON  */
+sbit at 0x8F TF1;
+sbit at 0x8E TR1;
+sbit at 0x8D TF0;
+sbit at 0x8C TR0;
+sbit at 0x8B IE1;
+sbit at 0x8A IT1;
+sbit at 0x89 IE0;
+sbit at 0x88 IT0;
+
+/*  IE   */
+sbit at 0xAF EA;
+sbit at 0xAC ES;
+sbit at 0xAB ET1;
+sbit at 0xAA EX1;
+sbit at 0xA9 ET0;
+sbit at 0xA8 EX0;
+
+/*  IP   */ 
+sbit at 0xBC PS;
+sbit at 0xBB PT1;
+sbit at 0xBA PX1;
+sbit at 0xB9 PT0;
+sbit at 0xB8 PX0;
+
+/*  P3  */
+sbit at 0xB7 RD;
+sbit at 0xB6 WR;
+sbit at 0xB5 T1;
+sbit at 0xB4 T0;
+sbit at 0xB3 INT1;
+sbit at 0xB2 INT0;
+sbit at 0xB1 TXD;
+sbit at 0xB0 RXD;
+
+/*  SCON  */
+sbit at 0x9F SM0;
+sbit at 0x9E SM1;
+sbit at 0x9D SM2;
+sbit at 0x9C REN;
+sbit at 0x9B TB8;
+sbit at 0x9A RB8;
+sbit at 0x99 TI;
+sbit at 0x98 RI;
+
+#endif /* _REG51SDCC_H_ */