ifndef Lib.mak.included
Lib.mak.included := 1
-# These variables should be provided by the includer Makefile:
+# These variables should be provided by the Makefile that include us:
# P should be the project name, mostly used to handle include directories
# T should be the path to the top-level directory.
# S should be sub-directory where the current makefile is, relative to $T.
# Default mode used to install files
IMODE ?= 0644
-# Degault install flags
+# Default install flags
IFLAGS ?= -D
-# Use precompiled headers if non-empty
+# Use pre-compiled headers if non-empty
GCH ?=
# Directories
##############
-# Base directory where to install files (can be overrided, should be absolute)
+# Base directory where to install files (can be overridden, should be absolute)
prefix ?= /usr/local
# Path to a complete alternative environment, usually a jail, or an installed
# Generated files top directory
G ?= $D/$F
-# Objects (and other garbage like precompiled headers and dependency files)
+# Objects (and other garbage like pre-compiled headers and dependency files)
# directory
O ?= $G/obj
# returns empty.
eq = $(if $(subst $1,,$2),,$1)
-# Find sources files and get the corresponding object names
-# The first argument should be the sources extension ("c" or "cpp" typically)
-# It expects the variable $T and $O to be defined as commented previously in
-# this file.
-find_objects = $(patsubst $T/%.$1,$O/%.o,$(shell find $C -name '*.$1'))
+# Find sources files and get the corresponding object names. The first
+# argument should be the sources extension ("c" or "cpp" typically). The
+# second argument is where to search for the sources ($C if omitted). The
+# resulting files will always have the suffix "o" and the directory rewritten
+# to match the directory structure (from $T) but in the $O directory. For
+# example, if $T is "/usr/src", $O is "/tmp/obj", $C is "/usr/src/curr" and it
+# have 2 C sources: "/usr/src/curr/1.c" and "/usr/src/curr/dir/2.c", the call:
+# $(call find_objects,c)
+# Will yield "/tmp/obj/curr/1.o" and "/tmp/obj/curr/dir/2.o".
+find_objects = $(patsubst $T/%.$1,$O/%.o,$(shell \
+ find $(if $2,$2,$C) -name '*.$1'))
# Find sources files and get the corresponding object names
# The first argument should be the sources extension ("c" or "cpp" typically)
# Link object files to build an executable. The objects files are taken from
# the prerequisite files ($O/%.o). If in the prerequisite files are shared
# objects ($L/lib%.so), they are included as libraries to link to (-l%). This
-# function is designed to be used as a command in a rule. The ouput name is
+# function is designed to be used as a command in a rule. The output name is
# taken from the rule automatic variables. If an argument is provided, it's
# included in the link command line. The variable LINKER is used to link the
# executable; for example, if you want to link a C++ executable, you should use
install_file = $(call exec,install -m $(if $1,$1,0644) $(if $2,$2,-D) \
$(if $3,$3,$<) $(if $4,$4,$@))
+# Concatenate variables together. The first argument is a list of variables
+# names to concatenate. The second argument is an optional prefix for the
+# variables and the third is the string to use as separator (" ~" if omitted).
+# For example:
+# X_A := a
+# X_B := b
+# $(call varcat,A B,X_, --)
+# Will produce something like "a -- b --"
+varcat = $(foreach v,$1,$($2$v)$(if $3,$3, ~))
+
+# Replace variables with specified values in a template file. The first
+# argument is a list of make variables names which will be replaced in the
+# target file. The strings @VARNAME@ in the template file will be replaced
+# with the value of the make $(VARNAME) variable and the result will be stored
+# in the target file. The second (optional) argument is a prefix to add to the
+# make variables names, so if the prefix is PREFIX_ and @VARNAME@ is found in
+# the template file, it will be replaced by the value of the make variable
+# $(PREFIX_VARNAME). The third and fourth arguments are the source file and
+# the destination file (both optional, $< and $@ are used if omitted). The
+# fifth (optional) argument are options to pass to the substitute sed command
+# (for example, use "g" if you want to do multiple substitutions per line).
+replace = $(call exec,sed '$(foreach v,$1,s|@$v@|$($2$v)|$5;)' $(if $3,$3,$<) \
+ > $(if $4,$4,$@))
+
# Create a symbolic link to the project under the $(INCLUDE_DIR). The first
-# argument is the name of symlink to create. The link is only created if it
-# doesn't already exist.
+# argument is the name of symbolic link to create. The link is only created if
+# it doesn't already exist.
symlink_include_dir = $(shell \
test -L $(INCLUDE_DIR)/$1 \
|| ln -s $C $(INCLUDE_DIR)/$1 )
echo "$2" > $1 ; fi)
-# Overrided flags
+# Overridden flags
##################
# Warn about everything
# Let the program know where it will be installed
override CPPFLAGS += -DPREFIX=$(prefix)
-# Be standard compilant
+# Be standard compliant
override CFLAGS += -std=c99 -pedantic
override CXXFLAGS += -std=c++98 -pedantic
$L/%.so: $G/link-o-flags
$(call link,-shared)
+# Create pkg-config files using a template
+$L/%.pc:
+ $(call replace,$(PC_VARS),$*-PC-)
+
# Install binary programs
$I/bin/%:
$(call install_file,0755)
$I/sbin/%:
$(call install_file,0755)
+# Install pkg-config specification files
+$I/lib/pkgconfig/%:
+ $(call install_file)
+
# Install libraries
$I/lib/%:
$(call install_file)
# sub-makes to add values to the special variables $(all), after this makefile
# was read.
.SECONDEXPANSION:
-
+
# Phony rule to make all the targets (sub-makefiles can append targets to build
# to the $(all) variable).
.PHONY: all
###################################
# Create $O, $B, $L and $(INCLUDE_DIR) directories and replicate the directory
-# structure of the project into $O. Create one symlink "last" to the current
-# build directory.
+# structure of the project into $O. Create one symbolic link "last" to the
+# current build directory.
#
# NOTE: the second mkdir can yield no arguments if the project don't have any
# subdirectories, that's why the current directory "." is included, so it
######################################################
# Re-compile C files if one of this variables changes
-COMPILE.c.FLAGS += $(CC) ~ $(CPPFLAGS) ~ $(CFLAGS) ~ $(TARGET_ARCH) ~ $(prefix)
+COMPILE.c.FLAGS := $(call varcat,CC CPPFLAGS CFLAGS TARGET_ARCH prefix)
# Re-compile C++ files if one of this variables changes
-COMPILE.cpp.FLAGS += $(CXX) ~ $(CPPFLAGS) ~ $(CXXFLAGS) ~ $(TARGET_ARCH) \
- ~ $(prefix)
+COMPILE.cpp.FLAGS := $(call varcat,CXX CPPFLAGS CXXFLAGS TARGET_ARCH prefix)
# Re-link binaries and libraries if one of this variables changes
-LINK.o.FLAGS += $(LD) ~ $(LDFLAGS) ~ $(TARGET_ARCH)
+LINK.o.FLAGS := $(call varcat,LD LDFLAGS TARGET_ARCH)
# Create files containing the current flags to trigger a rebuild if they change
setup_flag_files__ := $(call gen_rebuild_flags,$G/compile-c-flags, \
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