Pongo nombres más legibles a algunos bits de los registros.

diff --git a/pruebas/keil/red_test_anda/etherdev.c b/pruebas/keil/red_test_anda/etherdev.c
index 44c305b643ee1881234eb4448d2b9b62a50baccf..d07bf9809f6652107e557840fa473a2baf009457 100644 (file)
--- a/pruebas/keil/red_test_anda/etherdev.c
+++ b/pruebas/keil/red_test_anda/etherdev.c
@@ -120,7 +120,7 @@ bit etherdev_init(void)
     }
 
     // Stop RTL8019AS, select page 0 and abort DMA operation.
-    etherdev_reg_write(CR, RD2 | STP);
+    etherdev_reg_write(CR, ABORT | STP);
 
     // Initialise data configuration register. 
     // FIFO threshold 8 bytes, no loopback, don't use auto send packet.
@@ -134,7 +134,7 @@ bit etherdev_init(void)
     etherdev_reg_write(RCR, MON);
 
     // Initialise transmit configuration register to loopback internally.
-    etherdev_reg_write(TCR, LB0);
+    etherdev_reg_write(TCR, MODE1);
 
     // Clear interrupt status register bits by writing 1 to each.
     etherdev_reg_write(ISR, 0xFF);
@@ -147,7 +147,7 @@ bit etherdev_init(void)
     etherdev_reg_write(RBCR1, 0x00); 
     etherdev_reg_write(RSAR0, 0x00); // En la dirección 0x0000
     etherdev_reg_write(RSAR1, 0x00);
-    etherdev_reg_write(CR, RD0 | STA); // Comienza lectura
+    etherdev_reg_write(CR, READ | STA); // Comienza lectura
     uip_buf[6] = etherdev_reg_read(RDMA);
     etherdev_reg_read(RDMA); // Ignoramos porque viene como un word
     uip_buf[7] = etherdev_reg_read(RDMA);
@@ -165,7 +165,7 @@ bit etherdev_init(void)
     while(!(etherdev_reg_read(ISR) & RDC)) continue;
 
     // Abort/ complete DMA operation.
-    etherdev_reg_write(CR, RD2 | STP);
+    etherdev_reg_write(CR, ABORT | STP);
 
     // Limpia ISR
     etherdev_reg_write(ISR, RDC);
@@ -183,7 +183,7 @@ bit etherdev_init(void)
     etherdev_reg_write(PSTOP, ETH_RX_PAGE_STOP);
 
     // Select RTL8019AS register page 1.
-    etherdev_reg_write(CR, RD2 | PS0 | STP);
+    etherdev_reg_write(CR, ABORT | PAGE1 | STP);
 
     // Initialise current packet receive buffer page pointer
     etherdev_reg_write(CURR, ETH_RX_PAGE_START + 1);
@@ -197,13 +197,13 @@ bit etherdev_init(void)
     etherdev_reg_write(PAR5, uip_buf[11]);
 
     // Select RTL8019AS register page 0 and abort DMA operation.
-    etherdev_reg_write(CR, RD2 | STP);
+    etherdev_reg_write(CR, ABORT | STP);
 
     // Restart RTL8019AS. 
-    etherdev_reg_write(CR, RD2 | STA);
+    etherdev_reg_write(CR, ABORT | STA);
 
     // Initialise transmit configuration register for normal operation.
-    etherdev_reg_write(TCR, 0x00);
+    etherdev_reg_write(TCR, MODE0);
 
     // Receive configuration register to accept broadcast packets.
     etherdev_reg_write(RCR, AB);
@@ -227,7 +227,7 @@ void etherdev_send(void)
     // Setup for DMA transfer from uip_buf & uip_appdata buffers to RTL8019AS.
 
     // Select RTL8019AS register page 0 and abort DMA operation.
-    etherdev_reg_write(CR, RD2 | STA);
+    etherdev_reg_write(CR, ABORT | STA);
 
     // Wait until pending transmit operation completes.
     while(etherdev_reg_read(CR) & TXP) continue;
@@ -241,7 +241,7 @@ void etherdev_send(void)
     etherdev_reg_write(RBCR1, (unsigned char)(uip_len >> 8));
 
     // Initiate DMA transfer of uip_buf & uip_appdata buffers to RTL8019AS.
-    etherdev_reg_write(CR, RD1 | STA);
+    etherdev_reg_write(CR, WRITE | STA);
 
     // DMA transfer packet from uip_buf & uip_appdata to RTL8019AS local
     // transmit buffer memory.
@@ -257,7 +257,7 @@ void etherdev_send(void)
     etherdev_reg_write(ISR, RDC);
 
     // Abort/ complete DMA operation.
-    etherdev_reg_write(CR, RD2 | STA);
+    etherdev_reg_write(CR, ABORT | STA);
 
     // Set transmit page start to indicate packet start.
     etherdev_reg_write(TPSR, ETH_TX_PAGE_START);
@@ -273,7 +273,7 @@ void etherdev_send(void)
     etherdev_reg_write(TBCR1, (unsigned char)(uip_len >> 8));
 
     // Issue command for RTL8019AS to transmit packet from it's local buffer.
-    etherdev_reg_write(CR, RD2 | TXP | STA);
+    etherdev_reg_write(CR, ABORT | TXP | STA);
 
     return;
 }
@@ -288,7 +288,7 @@ static void etherdev_reset()
     // data it contains is uncorrupted, or will cause us grief.
 
     // Stop RTL8019AS and abort DMA operation.
-    etherdev_reg_write(CR, RD2 | STP);
+    etherdev_reg_write(CR, ABORT | STP);
 
     // Wait for controller to halt after any current tx completes.
     while(!(etherdev_reg_read(ISR) & RST)) continue;
@@ -309,10 +309,10 @@ static void etherdev_reset()
     }
 
     // Set transmit configuration register to loopback internally.
-    etherdev_reg_write(TCR, LB0);
+    etherdev_reg_write(TCR, MODE1);
 
     // Restart the RTL8019AS.
-    etherdev_reg_write(CR, RD2 | STA);
+    etherdev_reg_write(CR, ABORT | STA);
 
     // Re-initialise last receive buffer read pointer.
     etherdev_reg_write(BNRY, ETH_RX_PAGE_START);
@@ -330,12 +330,12 @@ static void etherdev_reset()
     etherdev_reg_write(ISR, PRX | OVW);
 
     // Re-itialise transmit configuration reg for normal operation.
-    etherdev_reg_write(TCR, 0x00);
+    etherdev_reg_write(TCR, MODE0);
 
     if(retransmit)
     {
         // Retransmit packet in RTL8019AS local tx buffer.
-        etherdev_reg_write(CR, RD2 | TXP | STA);
+        etherdev_reg_write(CR, ABORT | TXP | STA);
     }
 }
 
@@ -417,7 +417,7 @@ unsigned int etherdev_read(void)
         etherdev_reg_write(ISR, RDC);
 
         // Initiate DMA transfer of packet header.
-        etherdev_reg_write(CR, RD0 | STA);
+        etherdev_reg_write(CR, READ | STA);
 
         // Packet status.
         status = etherdev_reg_read(RDMA);
@@ -434,7 +434,7 @@ unsigned int etherdev_read(void)
         while(!(etherdev_reg_read(ISR) & RDC)) continue;
 
         // Abort/ complete DMA operation.
-        etherdev_reg_write(CR, RD2 | STA);
+        etherdev_reg_write(CR, ABORT | STA);
 
         // Limpia ISR
         etherdev_reg_write(ISR, RDC);
@@ -468,7 +468,7 @@ unsigned int etherdev_read(void)
             etherdev_reg_write(RBCR1, (unsigned char)(len >> 8));
 
             // Initiate DMA transfer of packet data.
-            etherdev_reg_write(CR, RD0 | STA);
+            etherdev_reg_write(CR, READ | STA);
 
             // Read packet data directly into uip_buf.
             uip_len = len;
@@ -485,7 +485,7 @@ unsigned int etherdev_read(void)
             while(!(etherdev_reg_read(ISR) & RDC)) continue;
 
             // Abort/ complete DMA operation.
-            etherdev_reg_write(CR, RD2 | STA);
+            etherdev_reg_write(CR, ABORT | STA);
 
             // Clear remote DMA complete interrupt status register bit.
             etherdev_reg_write(ISR, RDC);

diff --git a/pruebas/keil/red_test_anda/etherdev.h b/pruebas/keil/red_test_anda/etherdev.h
index 2f0c298881d58c6a290bf666a7750a3bf95a2f03..f683064d47c92e9cf44dbb9f73a1c269f80789d3 100644 (file)
--- a/pruebas/keil/red_test_anda/etherdev.h
+++ b/pruebas/keil/red_test_anda/etherdev.h
@@ -31,6 +31,15 @@ sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red
     #define TXP      0x04                  // Transmit packet bit
     #define STA      0x02                  // Start bit (a flag only)
     #define STP      0x01                  // Stop bit transceiver ctrl
+    // Shortcuts
+    #define PAGE0    0x00                  // Page 0
+    #define PAGE1    0x40                  // Page 1
+    #define PAGE2    0x80                  // Page 2
+    #define PAGE3    0xC0                  // Page 3 (Reserved!)
+    #define ABORT    0x20                  // Abort/Complete DMA
+    #define READ     0x08                  // Remote Read
+    #define WRITE    0x10                  // Remote Write
+    #define SENDPKT  0x18                  // Send Packet Command
 #define RDMA         0x10                  // Remote DMA port
 #define RESET        0x18                  // Reset port
 
@@ -87,6 +96,11 @@ sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red
     #define LB1      0x04                  // Loopback mode select bit 1
     #define LB0      0x02                  // Loopback mode select bit 0
     #define CRC      0x01                  // CRC generation inhibit bit
+    // Shortcuts
+    #define MODE0    0x00                  // Loopback mode 0
+    #define MODE1    0x02                  // Loopback mode 1
+    #define MODE2    0x04                  // Loopback mode 2
+    #define MODE3    0x06                  // Loopback mode 3
 #define DCR          ETH_REG_BASE + 0x0E   // Data configuration register
     // Data configuration register bits (write in page 0, read in page 2)
     #define FT1      0x40                  // FIFO threshold select bit 1