--- /dev/null
+/*--------------------------------------------------------------------------\r
+REG51.H\r
+\r
+ Header file for generic 80C51 and 80C31 microcontroller.\r
+\r
+--------------------------------------------------------------------------*/\r
+#ifndef REG51_H\r
+#define REG51_H\r
+\r
+/* BYTE Register */\r
+sfr P0 = 0x80;\r
+sfr P1 = 0x90;\r
+sfr P2 = 0xA0;\r
+sfr P3 = 0xB0;\r
+sfr PSW = 0xD0;\r
+sfr ACC = 0xE0;\r
+sfr B = 0xF0;\r
+sfr SP = 0x81;\r
+sfr DPL = 0x82;\r
+sfr DPH = 0x83;\r
+sfr PCON = 0x87;\r
+sfr TCON = 0x88;\r
+sfr TMOD = 0x89;\r
+sfr TL0 = 0x8A;\r
+sfr TL1 = 0x8B;\r
+sfr TH0 = 0x8C;\r
+sfr TH1 = 0x8D;\r
+sfr IE = 0xA8;\r
+sfr IP = 0xB8;\r
+sfr SCON = 0x98;\r
+sfr SBUF = 0x99;\r
+\r
+/* BIT Register */\r
+/* PSW */\r
+sbit CY = 0xD7;\r
+sbit AC = 0xD6;\r
+sbit F0 = 0xD5;\r
+sbit RS1 = 0xD4;\r
+sbit RS0 = 0xD3;\r
+sbit OV = 0xD2;\r
+sbit P = 0xD0;\r
+\r
+/* TCON */\r
+sbit TF1 = 0x8F;\r
+sbit TR1 = 0x8E;\r
+sbit TF0 = 0x8D;\r
+sbit TR0 = 0x8C;\r
+sbit IE1 = 0x8B;\r
+sbit IT1 = 0x8A;\r
+sbit IE0 = 0x89;\r
+sbit IT0 = 0x88;\r
+\r
+/* IE */\r
+sbit EA = 0xAF;\r
+sbit ES = 0xAC;\r
+sbit ET1 = 0xAB;\r
+sbit EX1 = 0xAA;\r
+sbit ET0 = 0xA9;\r
+sbit EX0 = 0xA8;\r
+\r
+/* IP */ \r
+sbit PS = 0xBC;\r
+sbit PT1 = 0xBB;\r
+sbit PX1 = 0xBA;\r
+sbit PT0 = 0xB9;\r
+sbit PX0 = 0xB8;\r
+\r
+/* P3 */\r
+sbit RD = 0xB7;\r
+sbit WR = 0xB6;\r
+sbit T1 = 0xB5;\r
+sbit T0 = 0xB4;\r
+sbit INT1 = 0xB3;\r
+sbit INT0 = 0xB2;\r
+sbit TXD = 0xB1;\r
+sbit RXD = 0xB0;\r
+\r
+/* SCON */\r
+sbit SM0 = 0x9F;\r
+sbit SM1 = 0x9E;\r
+sbit SM2 = 0x9D;\r
+sbit REN = 0x9C;\r
+sbit TB8 = 0x9B;\r
+sbit RB8 = 0x9A;\r
+sbit TI = 0x99;\r
+sbit RI = 0x98;\r
+\r
+#endif /* REG51_H */\r
--- /dev/null
+$NOMOD51\r
+;------------------------------------------------------------------------------\r
+; This file is part of the C51 Compiler package\r
+; Copyright (c) 1988-2002 Keil Elektronik GmbH and Keil Software, Inc.\r
+;------------------------------------------------------------------------------\r
+; STARTUP.A51: This code is executed after processor reset.\r
+;\r
+; To translate this file use A51 with the following invocation:\r
+;\r
+; A51 STARTUP.A51\r
+;\r
+; To link the modified STARTUP.OBJ file to your application use the following\r
+; BL51 invocation:\r
+;\r
+; BL51 <your object file list>, STARTUP.OBJ <controls>\r
+;\r
+;------------------------------------------------------------------------------\r
+;\r
+; User-defined Power-On Initialization of Memory\r
+;\r
+; With the following EQU statements the initialization of memory\r
+; at processor reset can be defined:\r
+;\r
+; ; the absolute start-address of IDATA memory is always 0\r
+IDATALEN EQU 80H ; the length of IDATA memory in bytes.\r
+;\r
+XDATASTART EQU 0H ; the absolute start-address of XDATA memory\r
+XDATALEN EQU 400H ; the length of XDATA memory in bytes.\r
+;\r
+PDATASTART EQU 0H ; the absolute start-address of PDATA memory\r
+PDATALEN EQU 0H ; the length of PDATA memory in bytes.\r
+;\r
+; Notes: The IDATA space overlaps physically the DATA and BIT areas of the\r
+; 8051 CPU. At minimum the memory space occupied from the C51 \r
+; run-time routines must be set to zero.\r
+;------------------------------------------------------------------------------\r
+;\r
+; Reentrant Stack Initilization\r
+;\r
+; The following EQU statements define the stack pointer for reentrant\r
+; functions and initialized it:\r
+;\r
+; Stack Space for reentrant functions in the SMALL model.\r
+IBPSTACK EQU 0 ; set to 1 if small reentrant is used.\r
+IBPSTACKTOP EQU 0FFH+1 ; set top of stack to highest location+1.\r
+;\r
+; Stack Space for reentrant functions in the LARGE model. \r
+XBPSTACK EQU 0 ; set to 1 if large reentrant is used.\r
+XBPSTACKTOP EQU 0FFFFH+1; set top of stack to highest location+1.\r
+;\r
+; Stack Space for reentrant functions in the COMPACT model. \r
+PBPSTACK EQU 0 ; set to 1 if compact reentrant is used.\r
+PBPSTACKTOP EQU 0FFFFH+1; set top of stack to highest location+1.\r
+;\r
+;------------------------------------------------------------------------------\r
+;\r
+; Page Definition for Using the Compact Model with 64 KByte xdata RAM\r
+;\r
+; The following EQU statements define the xdata page used for pdata\r
+; variables. The EQU PPAGE must conform with the PPAGE control used\r
+; in the linker invocation.\r
+;\r
+PPAGEENABLE EQU 0 ; set to 1 if pdata object are used.\r
+;\r
+PPAGE EQU 0 ; define PPAGE number.\r
+;\r
+PPAGE_SFR DATA 0A0H ; SFR that supplies uppermost address byte\r
+; (most 8051 variants use P2 as uppermost address byte)\r
+;\r
+;------------------------------------------------------------------------------\r
+\r
+; Standard SFR Symbols \r
+ACC DATA 0E0H\r
+B DATA 0F0H\r
+SP DATA 81H\r
+DPL DATA 82H\r
+DPH DATA 83H\r
+\r
+ NAME ?C_STARTUP\r
+\r
+\r
+?C_C51STARTUP SEGMENT CODE\r
+?STACK SEGMENT IDATA\r
+\r
+ RSEG ?STACK\r
+ DS 1\r
+\r
+ EXTRN CODE (?C_START)\r
+ PUBLIC ?C_STARTUP\r
+\r
+ CSEG AT 0\r
+?C_STARTUP: LJMP STARTUP1\r
+\r
+ RSEG ?C_C51STARTUP\r
+\r
+STARTUP1:\r
+\r
+IF IDATALEN <> 0\r
+ MOV R0,#IDATALEN - 1\r
+ CLR A\r
+IDATALOOP: MOV @R0,A\r
+ DJNZ R0,IDATALOOP\r
+ENDIF\r
+\r
+IF XDATALEN <> 0\r
+ MOV DPTR,#XDATASTART\r
+ MOV R7,#LOW (XDATALEN)\r
+ IF (LOW (XDATALEN)) <> 0\r
+ MOV R6,#(HIGH (XDATALEN)) +1\r
+ ELSE\r
+ MOV R6,#HIGH (XDATALEN)\r
+ ENDIF\r
+ CLR A\r
+XDATALOOP: MOVX @DPTR,A\r
+ INC DPTR\r
+ DJNZ R7,XDATALOOP\r
+ DJNZ R6,XDATALOOP\r
+ENDIF\r
+\r
+IF PPAGEENABLE <> 0\r
+ MOV PPAGE_SFR,#PPAGE\r
+ENDIF\r
+\r
+IF PDATALEN <> 0\r
+ MOV R0,#LOW (PDATASTART)\r
+ MOV R7,#LOW (PDATALEN)\r
+ CLR A\r
+PDATALOOP: MOVX @R0,A\r
+ INC R0\r
+ DJNZ R7,PDATALOOP\r
+ENDIF\r
+\r
+IF IBPSTACK <> 0\r
+EXTRN DATA (?C_IBP)\r
+\r
+ MOV ?C_IBP,#LOW IBPSTACKTOP\r
+ENDIF\r
+\r
+IF XBPSTACK <> 0\r
+EXTRN DATA (?C_XBP)\r
+\r
+ MOV ?C_XBP,#HIGH XBPSTACKTOP\r
+ MOV ?C_XBP+1,#LOW XBPSTACKTOP\r
+ENDIF\r
+\r
+IF PBPSTACK <> 0\r
+EXTRN DATA (?C_PBP)\r
+ MOV ?C_PBP,#LOW PBPSTACKTOP\r
+ENDIF\r
+\r
+ MOV SP,#?STACK-1\r
+; This code is required if you use L51_BANK.A51 with Banking Mode 4\r
+; EXTRN CODE (?B_SWITCH0)\r
+; CALL ?B_SWITCH0 ; init bank mechanism to code bank 0\r
+ LJMP ?C_START\r
+\r
+ END\r
--- /dev/null
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º TITLE: RTL8019AS ethernet routines for 8051 and º\r
+ º Keil C51 v7.00 port of Adam Dunkels' uIP v0.9 º\r
+ º FILENAME: etherdev.c º\r
+ º REVISION: VER 0.0 º\r
+ º REV.DATE: 21-01-05 º\r
+ º ARCHIVE: º\r
+ º AUTHOR: Copyright (c) 2005, Murray R. Van Luyn. º\r
+ º Refer to National Semiconductor DP8390 App Note 874. º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+\r
+/* ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿\r
+ ³ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS ³ \r
+ ³ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ³ \r
+ ³ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ³ \r
+ ³ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY ³ \r
+ ³ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ³ \r
+ ³ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ³ \r
+ ³ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ³ \r
+ ³ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ³ \r
+ ³ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ³ \r
+ ³ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ³ \r
+ ³ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ³ \r
+ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ */\r
+\r
+\r
+#include "etherdev.h"\r
+\r
+void sleep(unsigned char);\r
+\r
+static xdata leds1 _at_ 0x0080;\r
+static xdata leds2 _at_ 0x00c0;\r
+\r
+unsigned char uip_buf[64] =\r
+{\r
+ //0x00, 0x0c, 0x6e, 0x37, 0x19, 0xbf, // MAC destino\r
+ 0x00, 0x80, 0xc7, 0x42, 0x8d, 0x27, // MAC destino\r
+ 0x00, 0x0c, 0x6e, 0x37, 0x19, 0xbe, // MAC fuente\r
+ 0x00, 0x00, // Type\r
+};\r
+\r
+unsigned int uip_len = 14;\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º Private defines. º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+#define ETH_CPU_CLOCK ETH_CPU_XTAL / 12 // 8051 clock rate (X1 mode)\r
+\r
+// Delay routine timing parameters\r
+#define ETH_DELAY_CONST 9.114584e-5 // Delay routine constant\r
+#define ETH_DELAY_MULTPLR (unsigned char)(ETH_DELAY_CONST * ETH_CPU_CLOCK)\r
+\r
+// X1 CPU mode timing parameters\r
+#define ETH_T0_CLOCK ETH_CPU_XTAL / 12 // Timer 0 mode 1 clock rate\r
+#define ETH_T0_INT_RATE 24 // Timer 0 intrupt rate (Hz)\r
+#define ETH_T0_RELOAD 65536 - (ETH_T0_CLOCK / ETH_T0_INT_RATE)\r
+\r
+// Packet transmit & receive buffer configuration\r
+#define ETH_TX_PAGE_START 0x40 // 0x4000 Tx buffer is 6 * 256 = 1536 bytes\r
+#define ETH_RX_PAGE_START 0x46 // 0x4600 Rx buffer is 26 * 256 = 6656 bytes\r
+#define ETH_RX_PAGE_STOP 0x60 // 0x6000\r
+\r
+#define ETH_ADDR_PORT_MASK 0x1F // 00011111y\r
+#define ETH_DATA_PORT_MASK 0xFF // 11111111y\r
+\r
+#define ETH_MIN_PACKET_LEN 0x3C\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º Private Function Prototypes º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+static void etherdev_reg_write(unsigned char reg, unsigned char wr_data);\r
+static unsigned char etherdev_reg_read(unsigned char reg);\r
+static void etherdev_delay_ms(unsigned int count);\r
+static unsigned int etherdev_poll(void);\r
+//static void etherdev_timer0_isr(void) interrupt 1 using 1;\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º Private Macro Defines º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+// Manipulate PS1 & PS0 in CR to select RTL8019AS register page. \r
+#define ETHERDEV_SELECT_REG_PAGE(page) \\r
+ do \\r
+ { \\r
+ etherdev_reg_write(CR, etherdev_reg_read(CR) & ~(PS1 | PS0)); \\r
+ etherdev_reg_write(CR, etherdev_reg_read(CR) | (page << 6)); \\r
+ } while(0)\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º Global Variables º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+static unsigned char tick_count = 0;\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º Private Function Implementation º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º etherdev_reg_write() º\r
+ º º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+static void etherdev_reg_write(unsigned char reg, unsigned char wr_data)\r
+{\r
+ // Select register address.\r
+ ETH_ADDR_PORT &= ~ETH_ADDR_PORT_MASK; \r
+ ETH_ADDR_PORT |= reg;\r
+\r
+ // Output register data to port.\r
+ ETH_DATA_PORT = wr_data;\r
+\r
+ // Clock register data into RTL8019AS.\r
+ // IOR & IOW are both active low.\r
+ NICE = 0;\r
+ IOW = 0;\r
+ IOW = 1;\r
+ NICE = 1;\r
+\r
+ // Set register data port as input again.\r
+ ETH_DATA_PORT = ETH_DATA_PORT_MASK;\r
+\r
+ return;\r
+} \r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º etherdev_reg_read() º\r
+ º º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+static unsigned char etherdev_reg_read(unsigned char reg)\r
+{\r
+ unsigned char rd_data;\r
+\r
+ // Select register address.\r
+ ETH_ADDR_PORT &= ~ETH_ADDR_PORT_MASK;\r
+ ETH_ADDR_PORT |= reg;\r
+\r
+ // Enable register data output from RTL8019AS.\r
+ NICE = 0;\r
+ IOR = 0;\r
+\r
+ // Read register data from port.\r
+ rd_data = ETH_DATA_PORT;\r
+\r
+ // Disable register data output from RTL8019AS.\r
+ IOR = 1; \r
+ NICE = 1; \r
+\r
+ return rd_data;\r
+} \r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º etherdev_delay_ms() º\r
+ º º\r
+ º 1 to 255+ ms delay. º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+static void etherdev_delay_ms(unsigned int count)\r
+{\r
+\r
+ for(count *= ETH_DELAY_MULTPLR; count > 0; count--) continue;\r
+\r
+ return;\r
+}\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º etherdev_timer0_isr() º\r
+ º º\r
+ º This function is invoked each 1/24th of a second and updates a º\r
+ º 1/24th of a second tick counter. º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+static void etherdev_timer0_isr(void) interrupt 1 using 1\r
+{\r
+ // Reload timer/ counter 0 for 24Hz periodic interrupt. \r
+ TH0 = ETH_T0_RELOAD >> 8;\r
+ TL0 = ETH_T0_RELOAD;\r
+\r
+ // Increment 24ths of a second counter.\r
+ tick_count++;\r
+\r
+ return;\r
+}\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º Public Function Implementation º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º etherdev_init() º\r
+ º º\r
+ º Returns: 1 on success, 0 on failure. º\r
+ º Refer to National Semiconductor DP8390 App Note 874, July 1993. º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+bit etherdev_init(void)\r
+{\r
+ // Set IOR & IOW as they're active low.\r
+ IOR = 1;\r
+ IOW = 1;\r
+ NICE = 1;\r
+\r
+ // Set register data port as input.\r
+ ETH_DATA_PORT = ETH_DATA_PORT_MASK;\r
+\r
+#ifdef ETH_DEBUG\r
+ init_sio_poll();\r
+#endif /* ETH_DEBUG */\r
+\r
+ // Configure RTL8019AS ethernet controller.\r
+\r
+ // Keil startup code takes 4ms to execute (18.432MHz, X1 mode).\r
+ // That leaves plenty of time for the RTL8019AS to read it's\r
+ // configuration in from the 9346 EEPROM before we get here.\r
+\r
+ // Select RTL8019AS register page 0.\r
+ ETHERDEV_SELECT_REG_PAGE(0);\r
+\r
+ // Check if RTL8019AS fully reset.\r
+ if(!(etherdev_reg_read(ISR) & RST))\r
+ {\r
+leds1 = ~0xff;\r
+leds2 = ~0xff;\r
+while(1);\r
+ return 0;\r
+ }\r
+/*\r
+ // Select RTL8019AS register page 3.\r
+ ETHERDEV_SELECT_REG_PAGE(3);\r
+\r
+ // Temporarily disable config register write protection.\r
+ etherdev_reg_write(_9346CR, EEM1 | EEM0);\r
+\r
+ // Disable boot ROM & select 10BaseT with TP/CX auto-detect.\r
+ etherdev_reg_write(CONFIG2, BSELB);\r
+\r
+ // Select half-duplex, awake, power-up & LED_TX/ LED_RX/ LED_LNK behaviour.\r
+ etherdev_reg_write(CONFIG3, LEDS0);\r
+\r
+ // Re-enable config register write protection.\r
+ etherdev_reg_write(_9346CR, 0x00);\r
+*/\r
+ // Select RTL8019AS register page 0.\r
+ ETHERDEV_SELECT_REG_PAGE(0);\r
+\r
+ // Stop RTL8019AS, select page 0 and abort DMA operation.\r
+ etherdev_reg_write(CR, RD2 | STP);\r
+\r
+ // Initialise data configuration register. \r
+ // FIFO threshold 8 bytes, no loopback, don't use auto send packet.\r
+ etherdev_reg_write(DCR, FT1 | LS);\r
+\r
+ // Reset remote byte count registers.\r
+ etherdev_reg_write(RBCR0, 0x00);\r
+ etherdev_reg_write(RBCR1, 0x00);\r
+\r
+ // Receive configuration register to monitor mode.\r
+ etherdev_reg_write(RCR, MON);\r
+\r
+ // Initialise transmit configuration register to loopback internally.\r
+ etherdev_reg_write(TCR, LB0);\r
+\r
+ // Clear interrupt status register bits by writing 1 to each.\r
+ etherdev_reg_write(ISR, 0xFF);\r
+\r
+ // Mask all interrupts in mask register.\r
+ etherdev_reg_write(IMR, 0x00);\r
+\r
+ // Obtengo MAC de la placa\r
+ //etherdev_reg_write(CR, 0x21);\r
+\r
+\r
+ // Set transmit page start.\r
+ etherdev_reg_write(TPSR, ETH_TX_PAGE_START);\r
+\r
+ // Set receive buffer page start.\r
+ etherdev_reg_write(PSTART, ETH_RX_PAGE_START);\r
+\r
+ // Initialise last receive buffer read pointer.\r
+ etherdev_reg_write(BNRY, ETH_RX_PAGE_START);\r
+\r
+ // Set receive buffer page stop.\r
+ etherdev_reg_write(PSTOP, ETH_RX_PAGE_STOP);\r
+\r
+ // Select RTL8019AS register page 1.\r
+ etherdev_reg_write(CR, RD2 | PS0 | STP);\r
+\r
+ // Initialise current packet receive buffer page pointer\r
+ etherdev_reg_write(CURR, ETH_RX_PAGE_START);\r
+\r
+ // Set physical address\r
+ etherdev_reg_write(PAR0, 0x00);\r
+ etherdev_reg_write(PAR1, 0x0c);\r
+ etherdev_reg_write(PAR2, 0x6e);\r
+ etherdev_reg_write(PAR3, 0x37);\r
+ etherdev_reg_write(PAR4, 0x19);\r
+ etherdev_reg_write(PAR5, 0xbe);\r
+\r
+ // Select RTL8019AS register page 0 and abort DMA operation.\r
+ etherdev_reg_write(CR, RD2 | STP);\r
+\r
+ // Restart RTL8019AS. \r
+ etherdev_reg_write(CR, RD2 | STA);\r
+\r
+ // Initialise transmit configuration register for normal operation.\r
+ etherdev_reg_write(TCR, 0x00);\r
+\r
+ // Receive configuration register to accept broadcast packets.\r
+ etherdev_reg_write(RCR, AB);\r
+\r
+\r
+ // Initialize Timer 0 to generate a periodic 24Hz interrupt. \r
+\r
+ // Stop timer/ counter 0. \r
+ TR0 = 0; \r
+\r
+ // Set timer/ counter 0 as mode 1 16 bit timer. \r
+ TMOD &= 0xF0;\r
+ TMOD |= 0x01;\r
+\r
+ // Preload for 24Hz periodic interrupt. \r
+ TH0 = ETH_T0_RELOAD >> 8; \r
+ TL0 = ETH_T0_RELOAD;\r
+\r
+ // Restart timer/ counter 0 running.\r
+ TR0 = 1;\r
+\r
+ // Enable timer/ counter 0 overflow interrupt. \r
+ ET0 = 1;\r
+\r
+ // Enable global interrupt.\r
+ EA = 1;\r
+\r
+ return 1;\r
+}\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º etherdev_send() º\r
+ º º\r
+ º Send the packet in the uip_buf and uip_appdata buffers using the º\r
+ º RTL8019AS ethernet card. º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+void etherdev_send(void)\r
+{\r
+ unsigned int i;\r
+ unsigned char *ptr;\r
+\r
+ ptr = uip_buf;\r
+\r
+ // Setup for DMA transfer from uip_buf & uip_appdata buffers to RTL8019AS.\r
+\r
+ // Select RTL8019AS register page 0 and abort DMA operation.\r
+ etherdev_reg_write(CR, RD2 | STA);\r
+\r
+leds1 = ~0x01;\r
+i = etherdev_reg_read(CR);\r
+leds2 = ~i;\r
+ // Wait until pending transmit operation completes.\r
+ while(etherdev_reg_read(CR) & TXP) continue;\r
+\r
+ // Clear remote DMA complete interrupt status register bit.\r
+ etherdev_reg_write(ISR, RDC);\r
+\r
+ // Set remote DMA start address registers to indicate where to load packet.\r
+ etherdev_reg_write(RSAR0, 0x00);\r
+ etherdev_reg_write(RSAR1, ETH_TX_PAGE_START);\r
+\r
+ // Set remote DMA byte count registers to indicate length of packet load.\r
+ etherdev_reg_write(RBCR0, (unsigned char)(uip_len & 0xFF));\r
+ etherdev_reg_write(RBCR1, (unsigned char)(uip_len >> 8));\r
+\r
+ // Initiate DMA transfer of uip_buf & uip_appdata buffers to RTL8019AS.\r
+ etherdev_reg_write(CR, RD1 | STA);\r
+\r
+ // DMA transfer packet from uip_buf & uip_appdata to RTL8019AS local\r
+ // transmit buffer memory.\r
+ for(i = 0; i < uip_len; i++)\r
+ {\r
+ etherdev_reg_write(RDMA, *ptr++);\r
+ }\r
+\r
+ // Wait until remote DMA operation complete.\r
+leds1 = ~0x02;\r
+leds2 = ~etherdev_reg_read(ISR);\r
+ while(!(etherdev_reg_read(ISR) & RDC)) continue;\r
+\r
+ // Abort/ complete DMA operation.\r
+ etherdev_reg_write(CR, RD2 | STA);\r
+\r
+ // Set transmit page start to indicate packet start.\r
+ etherdev_reg_write(TPSR, ETH_TX_PAGE_START);\r
+\r
+ // Ethernet packets must be > 60 bytes, otherwise are rejected as runts.\r
+ if(uip_len < ETH_MIN_PACKET_LEN)\r
+ {\r
+ uip_len = ETH_MIN_PACKET_LEN;\r
+ }\r
+\r
+ // Set transmit byte count registers to indicate packet length.\r
+ etherdev_reg_write(TBCR0, (unsigned char)(uip_len & 0xFF));\r
+ etherdev_reg_write(TBCR1, (unsigned char)(uip_len >> 8));\r
+\r
+ // Issue command for RTL8019AS to transmit packet from it's local buffer.\r
+ etherdev_reg_write(CR, RD2 | TXP | STA);\r
+\r
+ return;\r
+}\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º etherdev_read() º\r
+ º º\r
+ º This function will read an entire IP packet into the uip_buf. º\r
+ º If it must wait for more than 0.5 seconds, it will return with º\r
+ º the return value 0. Otherwise, when a full packet has been read º\r
+ º into the uip_buf buffer, the length of the packet is returned. º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+unsigned int etherdev_read(void)\r
+{ \r
+ unsigned int bytes_read;\r
+\r
+ /* tick_count threshold should be 12 for 0.5 sec bail-out\r
+ One second (24) worked better for me, but socket recycling\r
+ is then slower. I set UIP_TIME_WAIT_TIMEOUT 60 in uipopt.h\r
+ to counter this. Retransmission timing etc. is affected also. */\r
+ while ((!(bytes_read = etherdev_poll())) && (tick_count < 12)) continue;\r
+\r
+ tick_count = 0;\r
+\r
+ return bytes_read;\r
+}\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º etherdev_poll() º\r
+ º º\r
+ º Poll the RTL8019AS ethernet device for an available packet. º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+static unsigned int etherdev_poll(void)\r
+{\r
+ unsigned int len = 0;\r
+\r
+ // Check if there is a packet in the rx buffer.\r
+ if(etherdev_reg_read(ISR) & PRX)\r
+ {\r
+ // Check if the rx buffer has overflowed.\r
+ if(etherdev_reg_read(ISR) & OVW)\r
+ {\r
+ bit retransmit = 0;\r
+\r
+ // If the receive buffer ring has overflowed we dump the whole\r
+ // thing and start over. There is no way of knowing whether the\r
+ // data it contains is uncorrupted, or will cause us grief.\r
+\r
+ // Stop RTL8019AS and abort DMA operation.\r
+ etherdev_reg_write(CR, RD2 | STP);\r
+\r
+ // Reset remote byte count registers.\r
+ etherdev_reg_write(RBCR0, 0x00);\r
+ etherdev_reg_write(RBCR1, 0x00);\r
+\r
+ // Wait for controller to halt after any current tx completes.\r
+ while(!(etherdev_reg_read(ISR) & RST)) continue;\r
+\r
+ // Check whether currently transmitting a packet.\r
+ if(etherdev_reg_read(CR) & TXP)\r
+ {\r
+ // If neither a successful transmission nor a tx abort error \r
+ // has occured, then flag current tx packet for resend.\r
+ if(!((etherdev_reg_read(ISR) & PTX)\r
+ || (etherdev_reg_read(ISR) & TXE)))\r
+ {\r
+ retransmit = 1;\r
+ }\r
+ }\r
+\r
+ // Set transmit configuration register to loopback internally.\r
+ etherdev_reg_write(TCR, LB0);\r
+\r
+ // Restart the RTL8019AS.\r
+ etherdev_reg_write(CR, RD2 | STA);\r
+\r
+ // Re-initialise last receive buffer read pointer.\r
+ etherdev_reg_write(BNRY, ETH_RX_PAGE_START);\r
+\r
+ // Select RTL8019AS register page 1.\r
+ ETHERDEV_SELECT_REG_PAGE(1);\r
+\r
+ // Re-initialise current packet receive buffer page pointer.\r
+ etherdev_reg_write(CURR, ETH_RX_PAGE_START);\r
+\r
+ // Select RTL8019AS register page 0.\r
+ ETHERDEV_SELECT_REG_PAGE(0);\r
+\r
+ // Clear rx buffer overflow & packet received interrupt flags.\r
+ etherdev_reg_write(ISR, PRX | OVW);\r
+\r
+ // Re-itialise transmit configuration reg for normal operation.\r
+ etherdev_reg_write(TCR, 0x00);\r
+ \r
+ if(retransmit)\r
+ {\r
+ // Retransmit packet in RTL8019AS local tx buffer.\r
+ etherdev_reg_write(CR, RD2 | TXP | STA);\r
+ }\r
+ }\r
+ else // Rx buffer has not overflowed, so read a packet into uip_buf.\r
+ {\r
+ unsigned int i;\r
+ unsigned char next_rx_packet;\r
+ unsigned char current;\r
+\r
+ // Retrieve packet header. (status, next_ptr, length_l, length_h)\r
+\r
+ // Clear remote DMA complete interrupt status register bit.\r
+ etherdev_reg_write(ISR, RDC);\r
+\r
+ // Set remote DMA start address registers to packet header.\r
+ etherdev_reg_write(RSAR0, 0x00);\r
+ etherdev_reg_write(RSAR1, etherdev_reg_read(BNRY));\r
+\r
+ // Set remote DMA byte count registers to packet header length.\r
+ etherdev_reg_write(RBCR0, 0x04);\r
+ etherdev_reg_write(RBCR1, 0x00);\r
+\r
+ // Initiate DMA transfer of packet header.\r
+ etherdev_reg_write(CR, RD0 | STA);\r
+\r
+ // Drop packet status. We don't use it.\r
+ etherdev_reg_read(RDMA);\r
+\r
+ // Save next packet pointer.\r
+ next_rx_packet = etherdev_reg_read(RDMA);\r
+\r
+ // Retrieve packet data length and subtract CRC bytes.\r
+ len = etherdev_reg_read(RDMA);\r
+ len += etherdev_reg_read(RDMA) << 8;\r
+ len -= 4;\r
+\r
+ // Wait until remote DMA operation completes.\r
+ while(!(etherdev_reg_read(ISR) & RDC)) continue;\r
+\r
+ // Abort/ complete DMA operation.\r
+ etherdev_reg_write(CR, RD2 | STA);\r
+\r
+\r
+ // Retrieve packet data.\r
+\r
+ // Check if incoming packet will fit into rx buffer.\r
+ if(len <= sizeof(uip_buf))\r
+ {\r
+ // Clear remote DMA complete interrupt status register bit.\r
+ etherdev_reg_write(ISR, RDC);\r
+\r
+ // Set remote DMA start address registers to packet data.\r
+ etherdev_reg_write(RSAR0, 0x04);\r
+ etherdev_reg_write(RSAR1, etherdev_reg_read(BNRY));\r
+\r
+ // Set remote DMA byte count registers to packet data length.\r
+ etherdev_reg_write(RBCR0, (unsigned char)(len & 0xFF));\r
+ etherdev_reg_write(RBCR1, (unsigned char)(len >> 8));\r
+\r
+ // Initiate DMA transfer of packet data.\r
+ etherdev_reg_write(CR, RD0 | STA);\r
+\r
+ // Read packet data directly into uip_buf.\r
+ for(i = 0; i < len; i++)\r
+ {\r
+ *(uip_buf + i) = etherdev_reg_read(RDMA);\r
+ }\r
+\r
+ // Wait until remote DMA operation complete.\r
+ while(!(etherdev_reg_read(ISR) & RDC)) continue;\r
+\r
+ // Abort/ complete DMA operation.\r
+ etherdev_reg_write(CR, RD2 | STA);\r
+\r
+ }\r
+ else\r
+ {\r
+ // Incoming packet too big, so dump it.\r
+ len = 0;\r
+ }\r
+\r
+ // Advance boundary pointer to next packet start.\r
+ etherdev_reg_write(BNRY, next_rx_packet);\r
+\r
+ // Select RTL8019AS register page 1.\r
+ ETHERDEV_SELECT_REG_PAGE(1);\r
+\r
+ // Retrieve current receive buffer page\r
+ current = etherdev_reg_read(CURR);\r
+\r
+ // Select RTL8019AS register page 0.\r
+ ETHERDEV_SELECT_REG_PAGE(0);\r
+\r
+ // Check if last packet has been removed from rx buffer.\r
+ if(next_rx_packet == current)\r
+ {\r
+ // Clear packet received interrupt flag.\r
+ etherdev_reg_write(ISR, PRX);\r
+ }\r
+ }\r
+ }\r
+\r
+ return len;\r
+}\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
+\r
--- /dev/null
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º TITLE: RTL8019AS ethernet routines for 8051 and º\r
+ º Keil C51 v7.00 port of Adam Dunkels' uIP v0.9 º\r
+ º FILENAME: etherdev.h º\r
+ º REVISION: VER 0.0 º\r
+ º REV.DATE: 21-01-05 º\r
+ º ARCHIVE: º\r
+ º AUTHOR: Copyright (c) 2005, Murray R. Van Luyn. º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+\r
+/* ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿\r
+ ³ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS ³ \r
+ ³ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ³ \r
+ ³ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ³ \r
+ ³ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY ³ \r
+ ³ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ³ \r
+ ³ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ³ \r
+ ³ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ³ \r
+ ³ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ³ \r
+ ³ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ³ \r
+ ³ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ³ \r
+ ³ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ³ \r
+ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ */\r
+\r
+\r
+#ifndef ETHERDEV_H\r
+#define ETHERDEV_H\r
+\r
+#include "REG51.h"\r
+\r
+extern unsigned char uip_buf[64];\r
+extern unsigned int uip_len;\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º Public defines. º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+// Change ETH_CPU_XTAL to match hardware\r
+#define ETH_CPU_XTAL 24000000 // 8051 crystal freq in Hz\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º ISA Expansion slot signal to 8051 port mapping. º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+#define ETH_DATA_PORT P2 // Adjust this to suit hardware.\r
+#define ETH_ADDR_PORT P1 // Adjust this to suit hardware.\r
+#define ETH_CTRL_PORT P3 // Adjust this to suit hardware.\r
+sbit IOW = ETH_CTRL_PORT^4; // ISA slot pin B13, RTL8019AS pin 30, active low\r
+sbit IOR = ETH_CTRL_PORT^5; // ISA slot pin B14, RTL8019AS pin 29, active low\r
+sbit NICE = ETH_CTRL_PORT^2; // A7, usado para activar placa de red\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º Required additional ISA slot wiring. º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+// SD0 ETH_DATA_PORT^0 // ISA slot pin A9, RTL8019AS pin 36\r
+// SD1 ETH_DATA_PORT^1 // ISA slot pin A8, RTL8019AS pin 37\r
+// SD2 ETH_DATA_PORT^2 // ISA slot pin A7, RTL8019AS pin 38\r
+// SD3 ETH_DATA_PORT^3 // ISA slot pin A6, RTL8019AS pin 39\r
+// SD4 ETH_DATA_PORT^4 // ISA slot pin A5, RTL8019AS pin 40\r
+// SD5 ETH_DATA_PORT^5 // ISA slot pin A4, RTL8019AS pin 41\r
+// SD6 ETH_DATA_PORT^6 // ISA slot pin A3, RTL8019AS pin 42\r
+// SD7 ETH_DATA_PORT^7 // ISA slot pin A2, RTL8019AS pin 43\r
+// SA0 ETH_ADDR_PORT^0 // ISA slot pin A31, RTL8019AS pin 5\r
+// SA1 ETH_ADDR_PORT^1 // ISA slot pin A30, RTL8019AS pin 7\r
+// SA2 ETH_ADDR_PORT^2 // ISA slot pin A29, RTL8019AS pin 8\r
+// SA3 ETH_ADDR_PORT^3 // ISA slot pin A28, RTL8019AS pin 9\r
+// SA4 ETH_ADDR_PORT^4 // ISA slot pin A27, RTL8019AS pin 10\r
+// SA5 GND // ISA slot pin A26, RTL8019AS pin 11\r
+// SA6 GND // ISA slot pin A25, RTL8019AS pin 12\r
+// SA7 GND // ISA slot pin A24, RTL8019AS pin 13\r
+// SA8 +5V // ISA slot pin A23, RTL8019AS pin 15\r
+// SA9 +5V // ISA slot pin A22, RTL8019AS pin 16\r
+// SA10 GND // ISA slot pin A21, RTL8019AS pin 18\r
+// SA11 GND // ISA slot pin A20, RTL8019AS pin 19\r
+// SA12 GND // ISA slot pin A19, RTL8019AS pin 20\r
+// SA13 GND // ISA slot pin A18, RTL8019AS pin 21\r
+// SA14 GND // ISA slot pin A17, RTL8019AS pin 22\r
+// SA15 GND // ISA slot pin A16, RTL8019AS pin 23\r
+// SA16 GND // ISA slot pin A15, RTL8019AS pin 24\r
+// SA17 GND // ISA slot pin A14, RTL8019AS pin 25\r
+// SA18 GND // ISA slot pin A13, RTL8019AS pin 26\r
+// SA19 GND // ISA slot pin A12, RTL8019AS pin 27\r
+// AEN GND // ISA slot pin A11, RTL8019AS pin 34\r
+// SMEMW +5V // ISA slot pin B11, RTL8019AS pin 32\r
+// SMEMR +5V // ISA slot pin B12, RTL8019AS pin 31\r
+// GND GND // ISA slot pin B1\r
+// +5VDC +5V // ISA slot pin B3\r
+// GND GND // ISA slot pin B31\r
+// +5VDC +5V // ISA slot pin B29\r
+// RESET ? // ISA slot pin B2, active high reset input\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º ISA 16 bit expansion slot edge connector. º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+\r
+// ³ ÚÄÄÄÄÄ¿ ³\r
+// ³C18 C1³ ³A31 Component side A1³\r
+// ÔÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ; ÔÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ; \r
+// D18 D1 B31 Solder side B1\r
+\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º RTL8019AS Register defines. º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+\r
+// Register base address\r
+#define ETH_REG_BASE 0x0000 // Hardwired to 0x0300\r
+\r
+// Registers common to all pages.\r
+#define CR ETH_REG_BASE + 0x00 // Control register\r
+ // Control register bits\r
+ #define PS1 0x80 // Page select bit 1\r
+ #define PS0 0x40 // Page select bit 0\r
+ #define RD2 0x20 // Remote DMA control bit 2\r
+ #define RD1 0x10 // Remote DMA control bit 1\r
+ #define RD0 0x08 // Remote DMA control bit 0\r
+ #define TXP 0x04 // Transmit packet bit\r
+ #define STA 0x02 // Start bit (a flag only)\r
+ #define STP 0x01 // Stop bit transceiver ctrl\r
+#define RDMA 0x10 // Remote DMA port\r
+#define RESET 0x18 // Reset port\r
+\r
+// Page 0 read/write registers.\r
+#define BNRY ETH_REG_BASE + 0x03 // Boundary register\r
+#define ISR ETH_REG_BASE + 0x07 // Interrupt status register\r
+ // Interrupt status register bits\r
+ #define RST 0x80 // Reset state indicator bit\r
+ #define RDC 0x40 // Remote DMA complete bit\r
+ #define CNT 0x20 // Network tally counter MSB set\r
+ #define OVW 0x10 // Receive buffer exhausted\r
+ #define TXE 0x08 // Transmit abort error bit\r
+ #define RXE 0x04 // Receive error report bit\r
+ #define PTX 0x02 // Successful packet transmit\r
+ #define PRX 0x01 // Successful packet receive\r
+\r
+// Page 0 read only registers.\r
+#define CLDA0 ETH_REG_BASE + 0x01\r
+#define CLDA1 ETH_REG_BASE + 0x02\r
+#define TSR ETH_REG_BASE + 0x04\r
+#define NCR ETH_REG_BASE + 0x05\r
+#define FIFO ETH_REG_BASE + 0x06\r
+#define CRDA0 ETH_REG_BASE + 0x08\r
+#define CRDA1 ETH_REG_BASE + 0x09\r
+#define _8019ID0 ETH_REG_BASE + 0x0A\r
+#define _8019ID1 ETH_REG_BASE + 0x0B\r
+#define RSR ETH_REG_BASE + 0x0C\r
+#define CNTR0 ETH_REG_BASE + 0x0D\r
+#define CNTR1 ETH_REG_BASE + 0x0E\r
+#define CNTR2 ETH_REG_BASE + 0x0F\r
+\r
+// Page 0 write only registers.\r
+#define PSTART ETH_REG_BASE + 0x01 // Receive page start register\r
+#define PSTOP ETH_REG_BASE + 0x02 // Receive page stop register\r
+#define TPSR ETH_REG_BASE + 0x04 // Transmit page start register\r
+#define TBCR0 ETH_REG_BASE + 0x05 // Transmit byte count register 0\r
+#define TBCR1 ETH_REG_BASE + 0x06 // Transmit byte count register 1\r
+#define RSAR0 ETH_REG_BASE + 0x08 // Remote start address register 0\r
+#define RSAR1 ETH_REG_BASE + 0x09 // Remote start address register 0\r
+#define RBCR0 ETH_REG_BASE + 0x0A // Remote byte count register 0\r
+#define RBCR1 ETH_REG_BASE + 0x0B // Remote byte count register 1\r
+#define RCR ETH_REG_BASE + 0x0C // Receive configuration register\r
+ // Receive configuration register bits (write in page 0, read in page 2)\r
+ #define MON 0x20 // Monitor mode select bit\r
+ #define PRO 0x10 // Promiscuous mode select bit\r
+ #define AM 0x08 // Multicast packet accept bit\r
+ #define AB 0x04 // Broadcast packet accept bit\r
+ #define AR 0x02 // Runt packet accept bit\r
+ #define SEP 0x01 // Error packet accept bit\r
+#define TCR ETH_REG_BASE + 0x0D // Transmit configuration register\r
+ // Transmit configuration register bits\r
+ #define OFST 0x10 // Collision offset enable bit\r
+ #define ATD 0x08 // Auto transmit disable select bit\r
+ #define LB1 0x04 // Loopback mode select bit 1\r
+ #define LB0 0x02 // Loopback mode select bit 0\r
+ #define CRC 0x01 // CRC generation inhibit bit\r
+#define DCR ETH_REG_BASE + 0x0E // Data configuration register\r
+ // Data configuration register bits (write in page 0, read in page 2)\r
+ #define FT1 0x40 // FIFO threshold select bit 1\r
+ #define FT0 0x20 // FIFO threshold select bit 0\r
+ #define ARM 0x10 // Auto-initialise remote\r
+ #define LS 0x08 // Loopback select bit\r
+ #define LAS 0x04 // Set to 0 (pwrup = 1)\r
+ #define BOS 0x02 // Byte order select bit\r
+ #define WTS 0x01 // Word transfer select bit\r
+#define IMR ETH_REG_BASE + 0x0F // Interrupt mask register\r
+ // Interrupt mask register bits\r
+ // Each enable bit correspons with an interrupt flag in ISR\r
+\r
+// Page 1 read/write registers.\r
+#define PAR0 ETH_REG_BASE + 0x01 // Physical address register 0\r
+#define PAR1 ETH_REG_BASE + 0x02 // Physical address register 1\r
+#define PAR2 ETH_REG_BASE + 0x03 // Physical address register 2\r
+#define PAR3 ETH_REG_BASE + 0x04 // Physical address register 3\r
+#define PAR4 ETH_REG_BASE + 0x05 // Physical address register 4\r
+#define PAR5 ETH_REG_BASE + 0x06 // Physical address register 5\r
+#define CURR ETH_REG_BASE + 0x07 // Current receive buffer page\r
+#define MAR0 ETH_REG_BASE + 0x08\r
+#define MAR1 ETH_REG_BASE + 0x09\r
+#define MAR2 ETH_REG_BASE + 0x0A\r
+#define MAR3 ETH_REG_BASE + 0x0B\r
+#define MAR4 ETH_REG_BASE + 0x0C\r
+#define MAR5 ETH_REG_BASE + 0x0D\r
+#define MAR6 ETH_REG_BASE + 0x0E\r
+#define MAR7 ETH_REG_BASE + 0x0F\r
+\r
+// Page 2 read only registers.\r
+// Each previously defined in page 0 write only.\r
+//#define PSTART ETH_REG_BASE + 0x01\r
+//#define PSTOP ETH_REG_BASE + 0x02\r
+//#define TPSR ETH_REG_BASE + 0x04\r
+//#define RCR ETH_REG_BASE + 0x0C\r
+//#define TCR ETH_REG_BASE + 0x0D\r
+//#define DCR ETH_REG_BASE + 0x0E\r
+//#define IMR ETH_REG_BASE + 0x0F\r
+\r
+// Page 3 read/write registers.\r
+#define _9346CR ETH_REG_BASE + 0x01 // 9346 EEPROM command register\r
+ // 9346 EEPROM command register bits\r
+ #define EEM1 0x80 // RTL8019AS operating mode bit 1\r
+ #define EEM0 0x40 // RTL8019AS operating mode bit 0\r
+ #define EECS 0x08 // 9346 EEPROM chip select bit\r
+ #define EESK 0x04 // 9346 EEPROM serial clock bit\r
+ #define EEDI 0x02 // 9346 EEPROM data input bit\r
+ #define EEDO 0x01 // 9346 EEPROM data output bit\r
+#define BPAGE ETH_REG_BASE + 0x02\r
+#define CONFIG1 ETH_REG_BASE + 0x04 // RTL9019AS config register 1\r
+ // RTL9019AS config register 1 bits\r
+ #define IRQEN 0x80 // IRQ enable bit (WR protected)\r
+ #define IRQS2 0x40 // IRQ line select bit 2\r
+ #define IRQS1 0x20 // IRQ line select bit 1\r
+ #define IRQS0 0x10 // IRQ line select bit 0\r
+ #define IOS3 0x08 // I/O base address select bit 3\r
+ #define IOS2 0x04 // I/O base address select bit 2\r
+ #define IOS1 0x02 // I/O base address select bit 1\r
+ #define IOS0 0x01 // I/O base address select bit 0\r
+#define CONFIG2 ETH_REG_BASE + 0x05 // \r
+ // RTL9019AS config register 2 bits\r
+ #define PL1 0x80 // Network medium type select bit 1\r
+ #define PL0 0x40 // Network medium type select bit 0\r
+ #define BSELB 0x20 // Boot ROM disable (WR protected)\r
+ #define BS4 0x10 // Boot ROM configuration bit 4\r
+ #define BS3 0x08 // Boot ROM configuration bit 3\r
+ #define BS2 0x04 // Boot ROM configuration bit 2\r
+ #define BS1 0x02 // Boot ROM configuration bit 1\r
+ #define BS0 0x01 // Boot ROM configuration bit 0\r
+#define CONFIG3 ETH_REG_BASE + 0x06 // RTL9019AS config register 3\r
+ // RTL9019AS config register 3 bits\r
+ #define PNP 0x80 // Plug & play mode indicator bit\r
+ #define FUDUP 0x40 // Full duplex mode select bit\r
+ #define LEDS1 0x20 // LED output select bit 1\r
+ #define LEDS0 0x10 // LED output select bit 0\r
+ #define SLEEP 0x04 // Sleep mode select bit\r
+ #define PWRDN 0x02 // Power down mode select bit\r
+ #define ACTIVEB 0x01 // Inverse of bit 0, PNP active reg\r
+\r
+// Page 3 read only registers.\r
+#define CONFIG0 ETH_REG_BASE + 0x03 // RTL9019AS config register 0\r
+ // RTL9019AS config register 0 bits\r
+ #define VERID1 0x80 // RTL9019AS version ID bit 1 (R/W)\r
+ #define VERID0 0x40 // RTL9019AS version ID bit 0 (R/W)\r
+ #define AUI 0x20 // AUI input pin state bit\r
+ #define PNPJP 0x10 // PNP jumper pin state bit\r
+ #define JP 0x08 // JP input pin state bit\r
+ #define BNC 0x04 // Thinnet mode indication bit\r
+#define CSNSAV ETH_REG_BASE + 0x08\r
+#define INTR ETH_REG_BASE + 0x0B\r
+#define CONFIG4 ETH_REG_BASE + 0x0D\r
+\r
+// Page 3 write only registers.\r
+#define TEST ETH_REG_BASE + 0x07\r
+#define HLTCLK ETH_REG_BASE + 0x09\r
+#define FMWP ETH_REG_BASE + 0x0C\r
+\r
+\r
+\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º Public Function Prototypes º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+bit etherdev_init(void);\r
+void etherdev_send(void);\r
+unsigned int etherdev_read(void);\r
+\r
+#endif\r
--- /dev/null
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º TITLE: Keil C51 v7.00 port of Adam Dunkels' uIP v0.9 º\r
+ º REVISION: VER 0.1 º\r
+ º REV.DATE: 30-01-05 º\r
+ º ARCHIVE: º\r
+ º AUTHOR: Murray R. Van Luyn, 2005. º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+\r
+/* ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿\r
+ ³ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS ³ \r
+ ³ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ³ \r
+ ³ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ³ \r
+ ³ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY ³ \r
+ ³ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ³ \r
+ ³ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ³ \r
+ ³ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ³ \r
+ ³ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ³ \r
+ ³ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ³ \r
+ ³ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ³ \r
+ ³ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ³ \r
+ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ */\r
+\r
+#include "main.h"\r
+\r
+static xdata leds1 _at_ 0x0080;\r
+static xdata leds2 _at_ 0x00c0;\r
+\r
+void sleep(unsigned char times)\r
+{\r
+ unsigned int i;\r
+ unsigned char j;\r
+ for (i = 0; i < 0xffff; ++i)\r
+ for (j = 0; j < times; ++j);\r
+}\r
+\r
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º º\r
+ º main() º\r
+ º º\r
+ º Simple Web Server test application. º\r
+ º º\r
+ º º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+void main(void)\r
+{\r
+ unsigned int len;\r
+ leds1 = ~0x00;\r
+ leds2 = ~0x00;\r
+ sleep(3);\r
+ /* Initialise the device driver. */ \r
+ if (!etherdev_init())\r
+ while(1); // Si falla init nos quedamos bobos\r
+\r
+ etherdev_send();\r
+ leds1 = ~0xaa;\r
+ leds2 = ~0xaa;\r
+\r
+\r
+ // leemos\r
+do\r
+{\r
+ len = etherdev_read();\r
+ if (len)\r
+ {\r
+ leds1 = ~0x55;\r
+ leds2 = len;\r
+ sleep(2);\r
+ for (len = 0; len < uip_len; ++len)\r
+ {\r
+ leds1 = ~(1 << (len % 8));\r
+ leds2 = ~uip_buf[len];\r
+ sleep(5);\r
+ }\r
+ leds1 = ~0x55;\r
+ leds2 = ~0x55;\r
+ }\r
+ else\r
+ {\r
+ leds1 = ~0xff;\r
+ leds2 = ~0xff;\r
+ }\r
+}\r
+while (1); // Quedamos paveando forever\r
+}\r
+\r
--- /dev/null
+/* ÉÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍ»\r
+ º TITLE: Keil C51 v7.00 port of Adam Dunkels' uIP v0.9 º\r
+ º REVISION: VER 0.0 º\r
+ º REV.DATE: 30-01-05 º\r
+ º ARCHIVE: º\r
+ º AUTHOR: Murray R. Van Luyn, 2005. º\r
+ ÈÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍÍͼ */\r
+\r
+/* ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿\r
+ ³ THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS ³ \r
+ ³ OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED ³ \r
+ ³ WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ³ \r
+ ³ ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY ³ \r
+ ³ DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL ³ \r
+ ³ DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE ³ \r
+ ³ GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS ³ \r
+ ³ INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, ³ \r
+ ³ WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING ³ \r
+ ³ NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS ³ \r
+ ³ SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. ³ \r
+ ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ */\r
+\r
+\r
+#ifndef MAIN_H\r
+#define MAIN_H\r
+\r
+#include "etherdev.h"\r
+\r
+#ifndef NULL\r
+#define NULL (void *)0\r
+#endif /* NULL */\r
+\r
+#endif /* MAIN_H */\r
--- /dev/null
+### uVision2 Project, (C) Keil Software\r
+### Do not modify !\r
+\r
+Target (Target 1), 0x0000 // Tools: 'MCS-51'\r
+\r
+Group (Source Group 1)\r
+\r
+File 1,5,<.\etherdev.h><etherdev.h> 0x0 \r
+File 1,1,<.\etherdev.c><etherdev.c> 0x0 \r
+File 1,5,<.\main.h><main.h> 0x0 \r
+File 1,1,<.\main.c><main.c> 0x0 \r
+File 1,2,<.\STARTUP.A51><STARTUP.A51> 0x0 \r
+File 1,5,<.\REG51.H><REG51.H> 0x0 \r
+\r
+\r
+Options 1,0,0 // Target 'Target 1'\r
+ Device (AT89S8252)\r
+ Vendor (Atmel)\r
+ Cpu (IRAM(0-0xFF) IROM(0-0x1FFF) CLOCK(24000000) MODA2)\r
+ FlashUt ()\r
+ StupF ("LIB\STARTUP.A51" ("Standard 8051 Startup Code"))\r
+ FlashDR ()\r
+ DevID ()\r
+ Rgf (REG8252.H)\r
+ Mem ()\r
+ C ()\r
+ A ()\r
+ RL ()\r
+ OH ()\r
+ DBC_IFX ()\r
+ DBC_CMS ()\r
+ DBC_AMS ()\r
+ DBC_LMS ()\r
+ UseEnv=0\r
+ EnvBin ()\r
+ EnvInc ()\r
+ EnvLib ()\r
+ EnvReg (ÿAtmel\)\r
+ OrgReg (ÿAtmel\)\r
+ TgStat=16\r
+ OutDir (.\)\r
+ OutName (red)\r
+ GenApp=1\r
+ GenLib=0\r
+ GenHex=1\r
+ Debug=1\r
+ Browse=0\r
+ LstDir (.\)\r
+ HexSel=0\r
+ MG32K=0\r
+ TGMORE=0\r
+ RunUsr 0 0 <>\r
+ RunUsr 1 0 <>\r
+ BrunUsr 0 0 <>\r
+ BrunUsr 1 0 <>\r
+ SVCSID <>\r
+ MODEL5=0\r
+ RTOS5=0\r
+ ROMSZ5=2\r
+ DHOLD5=0\r
+ XHOLD5=0\r
+ T51FL=208\r
+ XT51FL=0\r
+ CBANKS5=0\r
+ XBANKS5=0\r
+ RCB51 { 0,0,0,0,0,255,255,0,0 }\r
+ RXB51 { 0,0,0,0,0,0,0,0,0 }\r
+ OCM51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ OCR51 { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ IRO51 { 1,0,0,0,0,0,32,0,0 }\r
+ IRA51 { 0,0,0,0,0,0,1,0,0 }\r
+ XRA51 { 0,0,0,0,0,0,0,0,0 }\r
+ XRA512 { 0,0,0,0,0,0,0,0,0 }\r
+ IROM512 { 0,0,0,0,0,0,0,0,0 }\r
+ C51FL=21630224\r
+ C51VA=0\r
+ C51MSC ()\r
+ C51DEF ()\r
+ C51UDF ()\r
+ INCC5 ()\r
+ AX51FL=4\r
+ AX51MSC ()\r
+ AX51SET ()\r
+ AX51RST ()\r
+ INCA5 ()\r
+ PropFld { 0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0,0 }\r
+ IncBld=1\r
+ AlwaysBuild=0\r
+ GenAsm=0\r
+ AsmAsm=0\r
+ PublicsOnly=0\r
+ StopCode=3\r
+ CustArgs ()\r
+ LibMods ()\r
+ BankNo=65535\r
+ LX51FL=300\r
+ LX51OVL ()\r
+ LX51MSC ()\r
+ LX51DWN ()\r
+ LX51LFI ()\r
+ LX51ASN ()\r
+ LX51RES ()\r
+ LX51CCL ()\r
+ LX51UCL ()\r
+ LX51CSC ()\r
+ LX51UCS ()\r
+ LX51COB ()\r
+ LX51XDB ()\r
+ LX51PDB ()\r
+ LX51BIB ()\r
+ LX51DAB ()\r
+ LX51IDB ()\r
+ LX51PRC ()\r
+ LX51STK ()\r
+ LX51COS ()\r
+ LX51XDS ()\r
+ LX51BIS ()\r
+ LX51DAS ()\r
+ LX51IDS ()\r
+ OPTDL (S8051.DLL)()(DP51.DLL)(-p8252)(S8051.DLL)()(TP51.DLL)(-p8252)\r
+ OPTDBG 48125,0,()()()()()()()()()() ()()()()\r
+ FLASH1 { 1,0,0,0,0,0,0,0,255,255,255,255,0,0,0,0,0,0,0,0 }\r
+ FLASH2 ()\r
+ FLASH3 ()\r
+ FLASH4 ()\r
+EndOpt\r
+\r
--- /dev/null
+<html>\r
+<body>\r
+<pre>\r
+<h1>µVision3 Build Log</h1>\r
+<h2>Project:</h2>\r
+C:\Documents and Settings\labi\Mis documentos\6609\red\red.uv2\r
+Project File Date: 12/02/2005\r
+\r
+<h2>Output:</h2>\r
+Build target 'Target 1'\r
+compiling main.c...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=85.1 xdata=8 code=1303\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 4 Warning(s).\r
+Build target 'Target 1'\r
+compiling main.c...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=85.1 xdata=8 code=1309\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 4 Warning(s).\r
+Build target 'Target 1'\r
+compiling main.c...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=85.1 xdata=8 code=1309\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 4 Warning(s).\r
+Build target 'Target 1'\r
+compiling main.c...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=85.1 xdata=8 code=1289\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 4 Warning(s).\r
+Build target 'Target 1'\r
+compiling main.c...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=85.1 xdata=8 code=1309\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 4 Warning(s).\r
+Build target 'Target 1'\r
+compiling main.c...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=85.1 xdata=8 code=1303\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 4 Warning(s).\r
+Build target 'Target 1'\r
+compiling etherdev.c...\r
+compiling main.c...\r
+MAIN.C(28): error C141: syntax error near '=', expected ')'\r
+MAIN.C(65): error C202: 'ip_len': undefined identifier\r
+MAIN.C(68): error C202: 'ip_buf': undefined identifier\r
+Target not created\r
+Build target 'Target 1'\r
+compiling main.c...\r
+MAIN.C(59): error C202: 'i': undefined identifier\r
+MAIN.C(60): error C202: 'i': undefined identifier\r
+MAIN.C(63): error C202: 'i': undefined identifier\r
+MAIN.C(65): error C202: 'i': undefined identifier\r
+MAIN.C(67): error C202: 'i': undefined identifier\r
+MAIN.C(68): error C202: 'i': undefined identifier\r
+Target not created\r
+Build target 'Target 1'\r
+compiling main.c...\r
+MAIN.C(65): error C202: 'ip_len': undefined identifier\r
+MAIN.C(68): error C202: 'ip_buf': undefined identifier\r
+Target not created\r
+Build target 'Target 1'\r
+compiling etherdev.c...\r
+compiling main.c...\r
+MAIN.C(65): error C202: 'ip_len': undefined identifier\r
+MAIN.C(68): error C202: 'ip_buf': undefined identifier\r
+assembling STARTUP.A51...\r
+Target not created\r
+Build target 'Target 1'\r
+compiling main.c...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=81.1 xdata=8 code=1464\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 3 Warning(s).\r
+Build target 'Target 1'\r
+"red" - 0 Error(s), 0 Warning(s).\r
+Build target 'Target 1'\r
+compiling etherdev.c...\r
+compiling main.c...\r
+MAIN.C(46): warning C280: 'len': unreferenced local variable\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=87.1 xdata=8 code=1372\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 5 Warning(s).\r
+Build target 'Target 1'\r
+compiling etherdev.c...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=87.1 xdata=8 code=1354\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 4 Warning(s).\r
+Build target 'Target 1'\r
+compiling etherdev.c...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=87.1 xdata=8 code=1301\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 4 Warning(s).\r
+Build target 'Target 1'\r
+"red" - 0 Error(s), 0 Warning(s).\r
+Build target 'Target 1'\r
+compiling etherdev.c...\r
+compiling main.c...\r
+MAIN.C(46): warning C280: 'len': unreferenced local variable\r
+assembling STARTUP.A51...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=87.1 xdata=8 code=1301\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 5 Warning(s).\r
+Build target 'Target 1'\r
+compiling main.c...\r
+MAIN.C(46): warning C280: 'len': unreferenced local variable\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=87.1 xdata=8 code=1301\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 5 Warning(s).\r
+Build target 'Target 1'\r
+compiling main.c...\r
+MAIN.C(46): warning C280: 'len': unreferenced local variable\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=87.1 xdata=8 code=1301\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 5 Warning(s).\r
+Build target 'Target 1'\r
+compiling etherdev.c...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?ETHERDEV_READ?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=87.1 xdata=8 code=1319\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 4 Warning(s).\r
+Build target 'Target 1'\r
+compiling etherdev.c...\r
+compiling main.c...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=81.1 xdata=8 code=1464\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 3 Warning(s).\r
+Build target 'Target 1'\r
+compiling main.c...\r
+linking...\r
+*** WARNING L16: UNCALLED SEGMENT, IGNORED FOR OVERLAY PROCESS\r
+ SEGMENT: ?PR?_ETHERDEV_DELAY_MS?ETHERDEV\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 0080H\r
+ TO: 0081H\r
+*** WARNING L6: XDATA SPACE MEMORY OVERLAP\r
+ FROM: 00C0H\r
+ TO: 00C1H\r
+Program Size: data=81.1 xdata=8 code=1465\r
+creating hex file from "red"...\r
+"red" - 0 Error(s), 3 Warning(s).\r
+Build target 'Target 1'\r
+"red" - 0 Error(s), 0 Warning(s).\r
projects / z.facultad / 66.09 / etherled.git / commitdiff